Paper-to-engineering study | research snapshot 2026-07-11
Solving Analog CIM Problems in Hardware and Software
Analog compute-in-memory is not one architecture and accuracy is not one problem. SRAM charge-domain macros, RRAM crossbars, PCM tiles, embedded-flash arrays, and heterogeneous processors fail differently. The strongest papers recover useful accuracy by co-designing devices, circuits, converters, digital units, compilers, training, calibration, runtime maintenance, and validation.
CharacterizeMeasure real error distributions and corners
ContainFix high-cost errors near the device and converter
AdaptTrain, map, and calibrate for the measured target
MaintainTrack per-chip state, drift, faults, and fallback
Research verdict
The papers show scoped solutions, not a universal accuracy cure
Analog accuracy is now engineerable for selected models and operating conditions. NeuRRAM, IBM PCM systems, heterogeneous memristor/SRAM processors, and full-stack memristor platforms demonstrate that cross-layer mitigation can approach a declared software baseline. The 2026 reviews still identify variability, nonlinearity, drift, endurance, converters, parasitics, and mitigation overhead as active deployment barriers. A valid claim must name the workload, baseline, hardware boundary, calibration state, time horizon, chip population, and cost of every correction.
Industry test: Mythic's 2026 Videantis acquisition
See which accuracy mechanisms Mythic has disclosed, what the acquired digital architecture can actually solve, and what remains unproven.
System flow chart
Analog CIM is a lifecycle, not only a crossbar operation
The compiler prepares a device-aware artifact, deployment creates per-chip state, inference alternates between digital and analog engines, and maintenance feeds measured drift back into calibration. The four phases have different bottlenecks and must be measured separately.
Model and compiler
Programming and device state
Inference data path
Telemetry and recovery
- 1Reference modelFP baseline, task metrics, calibration data
- 2Quantize and hardenW4/W8 baseline, clipping, HWA noise, distillation
- 3Partition graphAnalog MVM, SRAM, digital engine, CPU fallback
- 4Physical loweringArrays, signed encoding, slices, ranges, partial sums
- 5Package artifactCommands, weight plan, calibration schema, debug map
- 1DiscoverRevision, healthy arrays, converter modes, firmware ABI
- 2Program weightsConductance targets, pulses, references, signed cells
- 3Write and verifyRetry, remap faults, reject weak cells or arrays
- 4CalibrateGain, offset, ADC range, saturation, temperature
- 5Bind stateFault map, calibration version, age, provenance
- 1Prepare activationDigital norm, scale, clip, tile, route
- 2DAC encodeStatic A8 range, voltage, pulse, or bit phases
- 3Analog MVMConductance products and physical column summation
- 4ADC readoutIntegrate, sense, quantize, detect saturation
- 5Digital finishHigh-precision partial sums, bias, residual, activation
- 6Check policyAccept, repeat, use higher fidelity, or fall back
Closed-loop maintenance
Telemetry → health vectors → drift/saturation decision → recalibrate, refresh, remap, or digital fallback → update the device-state bundle
For a 4-bit LLM, the 4-bit boundary normally belongs to weight storage, not to every arrow. A practical hybrid path is W4-like stored weights, 8-bit DAC inputs and ADC outputs, followed by higher-precision digital accumulation. The Analog Foundation Models study uses static 8-bit analog input/output boundaries, keeps attention and other digital work in FP16, and keeps the KV cache in FP16. Its result is evidence for hardware-aware adaptation, not a reason to build a 4-bit ADC and 4-bit accumulator.
Inference sequence diagram
One request crosses five ownership boundaries
The initialization messages run when a model is loaded. The layer loop repeats for every mapped graph region, and the recovery branch runs only when telemetry crosses a declared limit.
ApplicationModel and request
RuntimeSchedule and policy
Digital engineTensor preparation
CIM tileDAC, array, ADC
FirmwareCalibration and health
- Initialization and device binding
- Load compiled model artifact
- Discover revision, fault map, calibration age, and precision modes
- Program, write-verify, and calibrate tile
- Return verified device state to runtime
- Request and repeated layer/token loop
- Submit inputs and latency/accuracy policy
- Dispatch digital pre-processing and mapped region
- Normalize, scale, clip, tile, and quantize activations
- Send activation phases, array addresses, ADC range, and fidelity mode
- DAC encode → analog MVM → integrate → ADC convert
- Return partial sums, saturation flags, and counters
- Accumulate, rescale, add bias/residual, and run nonlinear work
- Layer result and telemetry
- Only when error, drift, or saturation exceeds policy
- Request recalibration, refresh, remap, repeat, or digital fallback
- Return updated state and recovery result
- Return output with trace and health status
CIM bottleneck map
The array MAC is fast; the system around it decides whether CIM wins
A bottleneck is not only the slowest stage. It can be the stage that sets the accuracy ceiling, dominates energy or area, prevents useful array utilization, or makes deployment and field maintenance too costly.
| Bottleneck | Where it appears | What you observe | First useful response | Cost moved elsewhere |
|---|---|---|---|---|
| ADC/DAC and sensing | Mixed-signal periphery before and after every array MVM. | Converter energy, area, latency, clipping, unused codes, or low effective precision dominate the array. | Layer-aware range selection, fewer active rows, adaptive thresholds, shared converters, or selectable precision phases. | More compiler state, calibration, serialization, phases, periphery, or reduced throughput. |
| Dot-product dynamic range | Column current, integrator, ADC, partial-sum path. | Four-bit weights still create outputs wider than four bits; long reductions saturate or lose small contributions. | Scale per layer/channel, split rows or bit slices, accumulate digitally at higher precision, and isolate outliers. | Extra passes, metadata, digital additions, SRAM traffic, and conversion energy. |
| Programming variation and hard faults | NVM conductance programming and physical cells. | Requested weights become distributions; stuck devices create structured, location-dependent error. | Write-verify, stable ranges, differential/offset encoding, spares, defect-aware placement, or factorization. | Longer load time, write energy, endurance use, redundant cells, capacity loss, or extra MVM stages. |
| Read noise and nonlinearity | Cell I-V behavior, sensing, integration, input-dependent array response. | Repeated MVMs vary, and error changes with signal magnitude or activation pattern. | Measured-noise HWA training, lower read voltage, references, averaging, weight expansion, or digital routing. | Training cost, lower signal-to-noise ratio, repeated reads, extra cells, or lower performance. |
| IR drop and parasitics | Long wordlines/bitlines, drivers, access devices, large crossbars. | The same weight behaves differently by position; larger arrays diverge from ideal matrix multiplication. | Smaller subarrays, stronger/local drivers, access devices, IR-aware mapping, and active-row limits. | More tiles, ADCs, routes, buffers, partial sums, area, and interconnect energy. |
| Drift, retention, and PVT | Stored conductance and analog circuits over time, voltage, and temperature. | A deployment that passed qualification gradually loses margin or changes after thermal events. | Reference rows, sensors, guardbands, drift-aware training, health vectors, recalibration, and selective refresh. | Maintenance traffic, downtime, calibration storage, refresh energy, endurance, and fleet complexity. |
| Activation delivery | Input buffers, DACs, pulse/bit phases, routing to rows. | The array waits for serialized multibit activations or consumes energy repeatedly charging lines. | Local SRAM, broadcast/reuse, pulse-width encoding, phase overlap, sparsity, and input pruning. | Larger buffers and control, restricted formats, model changes, or more difficult scheduling. |
| Partial sums and output movement | Across subarrays, tiles, chips, SRAM, NoC, and host boundaries. | Peak macro TOPS/W looks high while end-to-end latency and energy are dominated by reduction and transport. | Local accumulation, fusion, hierarchy-aware tiling, route scheduling, and keeping dependent work near the tile. | Digital area, SRAM capacity, synchronization, compiler complexity, and less flexible placement. |
| Mapping and utilization | Mismatch between model shapes and fixed physical rows, columns, capacity, and healthy arrays. | Padded rows, fragmented weights, replicated tensors, idle columns, load imbalance, or insufficient on-chip capacity. | Shape-aware packing, replication only when beneficial, structured sparsity, heterogeneous placement, and utilization-aware cost models. | Compilation search time, model restrictions, duplicated storage, or lower theoretical density. |
| Unsupported and sensitive operations | Softmax, normalization, nonlinearities, dynamic attention, KV cache, control, and numerically fragile layers. | Frequent analog/digital boundaries erase gains or low precision degrades task accuracy. | Digital/SRAM engines, operator fusion, mixed precision, sensitivity-based partitioning, and a clean fallback ABI. | More silicon, duplicated capabilities, conversions, scheduling dependencies, and software surface area. |
| Programming and model updates | Cold start, model replacement, fine-tuning, recovery, and fleet rollout. | Slow high-voltage writes, erase granularity, endurance limits, and long deployment windows. | Weight-stationary serving, immutable analog regions, transactional programming, staged rollout, and digital adapters. | Reduced update flexibility, extra digital memory, operational tooling, rollback storage, and version management. |
| Calibration and validation | Manufacturing, deployment, runtime maintenance, and product qualification. | Per-chip tuning and broad corner testing cost more than the steady-state kernel and delay release. | Automated calibration, compact device-state bundles, representative health vectors, correlation ladders, and explicit evidence levels. | Telemetry, storage, test time, simulator ownership, production infrastructure, and support cost. |
Critical-path rule
Optimize in this order: prevent saturation and illegal mappings, meet task accuracy, remove converter and movement stalls, improve utilization, then reduce calibration and lifecycle cost. Optimizing the crossbar MAC first can improve a number that is not limiting the product.
Architecture taxonomy
"NPU on RAM" hides several fundamentally different machines
The memory device determines how a weight is stored. The compute domain determines how products are formed and accumulated. Those choices set the failure mechanisms that software must model.
| Architecture | Weight and compute | Main strength | Dominant problems | Software consequence |
|---|---|---|---|---|
| Analog SRAM CIM | Digital bits in 6T/8T/9T cells gate current or redistribute charge on bitlines and capacitors. | Mature CMOS, fast writes, high endurance, no conductance drift. | Large cell area, volatility, model-load energy, mismatch, charge leakage, PVT sensitivity, ADC precision. | Bit slicing, ADC/row-count selection, PVT-aware calibration, frequent weight loading, and memory-capacity planning. |
| RRAM / memristor crossbar | Conductance stores a multilevel weight; voltage or pulse width times conductance creates current; columns sum by physics. | Dense non-volatile weights, high parallelism, compact 1T1R arrays. | Stochastic programming, stuck cells, nonlinear I-V, relaxation, IR drop, read noise, endurance, limited conductance range. | Write-verify, defect maps, differential or offset encoding, hardware-aware training, chip-in-loop tuning, and IR-aware placement. |
| PCM crossbar | Phase state controls conductance; pulse-width inputs integrate current into capacitors before time/digital conversion. | Dense backend-integrated weight storage and proven multicore/multichip demonstrations. | Programming error, conductance drift, read noise, asymmetry, slow/energy-heavy writes, weight-stationary execution. | Multi-device weight expansion, optimized programming, HWA training, per-column calibration, recalibration, and strict weight lifecycle. |
| Embedded-flash CIM | Floating-gate or charge-trap threshold stores an analog weight; read currents perform dense MVM. | Mature non-volatile storage, long retention, high density, useful for fixed inference weights. | High-voltage and slow programming, limited endurance, erase granularity, charge variation, asymmetric updates. | Offline compilation, infrequent programming, verify-and-calibrate deployment, immutable-weight artifacts, and digital fallback. |
| Heterogeneous mixed CIM | Memristor/PCM handles tolerant dense work; SRAM or digital units handle sensitive layers, kernels, reductions, and control. | Accuracy and flexibility without forcing every operation through the weakest analog regime. | Partitioning, format conversion, duplicated storage, routing, scheduling, wakeup, and a larger control plane. | Sensitivity analysis, layer/kernel placement, mixed INT/FP formats, conversion-aware scheduling, and end-to-end cost modeling. |
Digital CIM is a separate escape route. It can provide exact low-bit arithmetic inside SRAM, RRAM, or MRAM, avoiding analog error at the cost of more bit-level operations, addition circuitry, and often lower density or energy advantage. The 2025 mixed processor uses this principle: route sensitive work to lossless SRAM-CIM or tiny digital units instead of demanding that memristor CIM become exact.
Primary-paper solution ledger
What each architecture changed, and what remained outside the claim
Filter by memory or contribution. "Measured" does not always mean a complete end-to-end product; the boundary is stated on each card.
22-nm charge-domain SRAM CIM
Problem: multibit analog SRAM normally loses precision through mismatch, parasitics, noise, and converter cost.
Hardware: a passive C-2C charge ladder, 9T SRAM, local weight multiplexing, and an 8-bit MAC design target linearity across PVT.
Software: circuit and system analysis selects precision and validates the analog error budget; weights remain ordinary digital SRAM bits.
Evidence: 32.2 TOPS/W peak, less than 0.5% MVM error, and less than 1% measured error deviation across PVT.
Boundary: macro evidence, not a full model-to-runtime system; SRAM remains volatile and area intensive.
NeuRRAM RRAM chip
Problem: wire/driver drop, programming resolution, relaxation, coupling, and limited ADC range made software-only simulation optimistic.
Hardware: 48 reconfigurable cores, transposable dataflow, differential signed weights, and voltage-mode neuron sensing improve utilization and dynamic range.
Software: model-driven calibration, measured-noise training, continuous analog programming, and progressive chip-in-loop fine-tuning.
Evidence: complete hardware runs reached 99.0% MNIST, 85.7% CIFAR-10, and 84.7% Google speech-command accuracy.
Boundary: FPGA supplied intermediate buffers and partial sums; peak array efficiency excludes intermediate transfer.
Gradient descent-based PCM programming
Problem: cell-wise write-verify depends on precise low-current reads and can miss array nonlinearities that determine the actual MVM result.
Hardware: two 14-nm PCM cores, each with a 256 x 256 array, execute random-probe MVMs during deployment calibration.
Software: gradient descent minimizes measured MVM error and adjusts programming pulses, even when the best physical conductances differ from nominal weight targets.
Evidence: a scaled ResNet-9 hardware run improved from 84.75% to 86.01% CIFAR-10 accuracy; the programming-error advantage persisted for 24 hours.
Boundary: digital gradient calculation and non-MVM work remained off-array; repeated writes cost time and endurance, and each method received one complete inference run.
64-core PCM inference chip
Problem: an analog tile alone cannot execute activations, communication, convolution support, or complete LSTM layers.
Hardware: 64 PCM AIMC cores, an on-chip communication network, and digital activation/processing units form a complete mixed-signal data path.
Software: mapping and precision modes select one-phase high-throughput or four-phase high-precision MVM execution.
Evidence: near-software accuracy on ResNet and LSTM, with 2.48 TOPS/W high-precision or 9.76 TOPS/W low-precision modes.
Boundary: accuracy and efficiency still depend on model mapping, device programming, and the selected precision mode.
PCM speech recognition and transcription chip
Problem: large speech models amplify programming error, offset, saturation, and cross-tile movement; NVM writes are slow and finite-endurance.
Hardware: 34-tile chips, four PCM devices per cell, an AB differential method, bias rows, pulse-duration routing, and five chips for RNNT.
Software: HWA training and input pruning for KWS; calibration and per-column rescaling; weight expansion for the 45-million-weight RNNT.
Evidence: KWS measured 86.14% versus 86.75%; RNNT measured 9.258% WER versus 7.452% FP baseline.
Boundary: RNNT intermediate data and auxiliary computation used an x86 host; the chip lacked product digital cores and SRAM.
Memristor, SRAM, and digital mixed CIM
Problem: memristor CIM is dense but variation sensitive; lossless SRAM CIM is accurate but large and volatile.
Hardware: memristor-CIM, SRAM-CIM, tiny digital units, and INT/FP modes coexist on one edge processor.
Software: layer- and kernel-granular sensitivity analysis partitions work by error tolerance and format requirements.
Evidence: less than 0.45% degradation with 40.91 TFLOPS/W on ResNet-20/CIFAR-100 and 28.63 TFLOPS/W on MobileNet-v2/ImageNet.
Boundary: accuracy is preserved by heterogeneous routing, not by eliminating analog variation.
ALBERT on a 14-nm PCM chip
Problem: transformer projections have task-dependent sensitivity, shared weights see different activation distributions, and PCM drifts with time.
Hardware: 35 million PCM devices, 34 tiles, multi-device weight encoding, and a 2D mesh store all 7.1 million unique ALBERT weights.
Software: task-specific HWA noise fine-tuning, mapping, per-use column scale/offset calibration, and periodic recalibration.
Evidence: HWA improved average measured GLUE accuracy by 4.4%; recalibration reduced long-term drift loss.
Boundary: attention, GELU, softmax, layer normalization, pooling, and classification ran in software; some tasks used representative subsets.
OpenCIMTC full-stack memristor system
Problem: fixed hardware dataflow, manual placement, and manual parameter tuning prevent diverse models from deploying reliably.
Hardware: eight flexible memristor chips plus FPGA/CPU control support signed inputs/weights, multiple mappings, and model-dependent dataflows.
Software: CIM IR, compiler, simulator, optimizer, automatic placement, post-deployment training, and inference-time parameter search.
Evidence: six models across four tasks ran automatically; optimizations improved inference accuracy by 3.32% to 9.45%.
Boundary: a research platform with FPGA control, but unusually strong evidence for an actual compiler-optimizer-hardware loop.
Adaptive memristor ADC
Problem: uniform low-bit ADCs waste codes on layer-specific output distributions; high-bit ADCs dominate area and energy.
Hardware: analog-CAM quantization cells implement programmable overlapping thresholds, one-step conversion, recalibration, and paired-ADC super-resolution.
Software: layer statistics and a constrained Lloyd-Max optimization choose thresholds; program-and-verify maps them to conductance.
Evidence: fabricated 8x8 devices support the model; 5-bit VGG8 reached 89.55% under measured variation and system studies report lower ADC overhead.
Boundary: not a complete fabricated CIM accelerator; Q-cell count grows exponentially at high resolution.
Fault-free analogue computing
Problem: stuck-on/off cells create structured errors that redundancy or retraining may not remove efficiently.
Hardware: two cascaded programmable submatrices and optional compensation layers implement an indirect target matrix and eliminate differential pairs.
Software: gradient-based hardware-aware matrix decomposition uses the measured defect map and hardware constraints.
Evidence: over 99.999% DFT cosine similarity at 39% device faults and a 56-fold wireless bit-error-rate reduction.
Boundary: solves static representation faults for tested matrices; random read noise, ADC error, drift, nonlinear arrays, and complete DNN accuracy remain.
Hardware-aware training across model families
Problem: approximate MVM includes nonlinear and nondeterministic errors that ordinary FP or quantized training never sees.
Hardware abstraction: a realistic crossbar model includes weight, input, output, converter, and circuit nonidealities.
Software: retraining injects the target error model and searches robust operating points for CNNs, recurrent networks, and transformers.
Evidence: many evaluated models recovered floating-point iso-accuracy in simulation; input/output noise was often more damaging than weight noise.
Boundary: simulation evidence depends on model fidelity and does not replace silicon population and lifetime testing.
Unified heterogeneous AIMC mapping workflow
Problem: analog/digital assignment is combinatorial, existing methods use incompatible assumptions, and coarse first/last-layer rules do not capture decoder-transformer sensitivity.
Hardware abstraction: PCM-calibrated noise, 512 x 512 tiling, roughly 8-bit converters, digital compute units, memory, interconnect, and maintenance costs.
Software: characterize hardware, profile projection sensitivity, optimize architecture-aware mapping, then validate the complete system.
Evidence: four of 49 GPT-2-small projections dominated marginal sensitivity; 40 had modeled perplexity increase below 3 and became analog candidates.
Boundary: only workflow stages 1-2 were executed; no joint mapping, measured chip, runtime drift response, or end-to-end energy and latency result was produced.
Deep read 1 | measured IBM PCM hardware
Program the measured function, not each cell in isolation
This IEDM paper is the stronger of the two additions because it evaluates the method on fabricated 14-nm PCM cores. Its central lesson belongs in deployment firmware and the compiler/runtime contract.
New idea: conventional write-verify tries to make every read conductance equal its nominal target. Gradient descent-based programming instead minimizes the error of the complete on-chip MVM. It can intentionally leave individual readout weights farther from their nominal values when that compensates peripheral nonlinearity and improves the function the application actually consumes.
1. InitializeRoughly program the target matrix with a short iterative sequence or one-shot pulses.
2. ProbeGenerate synthetic random vectors and execute a batch of MVMs on the physical array; no application dataset is required.
3. Measure lossCompare measured outputs with the ideal target-matrix outputs and minimize normalized MVM error rather than individual-cell error.
4. Update pulsesCompute the gradient digitally, convert it into bounded SET/RESET pulse changes, program selected cells, and repeat.
What the result establishes
- Accurate single-device reads are not required when the array can execute MVM probes during programming.
- Function-level optimization can absorb small static nonlinearities that cell-wise conductance matching ignores.
- Random inputs generalized across tested input distributions and sparsity levels.
- Batch sizes of at least 64 beat the baseline; 256 or more performed best in the reported sweep.
What remains unresolved
- Digital gradient computation scales with probe batch, rows, and columns and adds deployment time.
- Repeated programming pulses consume energy and endurance; the paper does not provide a product lifetime budget.
- The experiment does not remove random read noise, ADC energy, saturation, PVT variation, or unsupported digital operators.
- One network and one complete inference run per programming method are not population-level qualification.
Deep read 2 | June 2026 architecture preprint
Profile transformer projections before searching the analog/digital mapping
This paper is current and directly relevant to the software stack, but its GPT-2 result is modeled rather than measured. The useful contribution is a disciplined workflow and a finer mapping granularity.
New idea: a decoder transformer should not be mapped by a blanket first/last-layer rule or by assigning an entire block to one engine. Sensitivity can differ sharply among Q/K/V, attention-output, and FFN projections in the same block. Projection-level profiling first reduces the search space, after which a hardware-specific optimizer can choose the actual analog/digital assignment.
What is genuinely useful
- The four-stage workflow prevents sensitivity profiling from being confused with final system mapping.
- GPT-2 sensitivity was concentrated, and the largest outlier was an internal block-0 attention-output projection.
- Projection granularity aligns with transformer datapaths while avoiding weight-level routing complexity.
- The profile can seed heuristic, analytical, or trainable Stage 3 mapping algorithms.
What must happen next
- Run Stage 3 jointly: one-at-a-time perturbation does not capture interacting errors from many analog projections.
- Run Stage 4 on a concrete accelerator and count converters, KV cache, memory, communication, latency, and energy.
- Validate the ranking on silicon, across PCM, ReRAM, and SRAM models, and after time-dependent drift.
- Repeat on larger decoder models; GPT-2-small does not prove that the same four projections dominate at scale.
Failure-to-solution explorer
Place each fix at the cheapest layer that can actually remove the error
The written conductance is not the requested weight
Hardware layerIterative write-verify, array-level random-probe MVMs, multi-device weights, reference cells, spare rows/columns, and defect characterization.
Compiler and trainingDifferential/offset encoding, defect-aware placement, function-level programming loss, optimized pulse targets, post-deployment training, and matrix factorization for severe static faults.
RuntimeBind the executable to a device fault map, run cell-wise verification or gradient-based MVM calibration, reject weak arrays, and preserve programming provenance.
TradeoffMore devices, probes, digital optimization, programming pulses, artifact state, deployment time, and endurance consumption.
The same MVM produces a distribution, not an exact value
Hardware layerLow-noise sensing, linear read voltage, voltage-mode readout, differential/AB methods, averaging, integration-time control, and weight expansion.
Training layerInject measured weight, input, output, and activation noise; clip outliers; tune noise scale per task; use chip-in-loop data when the model is incomplete.
RuntimeMonitor repeated-read variance and saturation, select a precision mode, and route sensitive regions to SRAM or digital units.
TradeoffLonger latency, duplicated weights, lower signal range, more digital work, and model-specific retraining.
ADC and DAC choices can erase the array advantage
Hardware layerShared or per-column converters, pulse-width inputs, multiple precision phases, voltage-mode normalization, programmable thresholds, bias rows, and converter recalibration.
Compiler layerProfile layer/channel distributions, assign ranges and bit widths, split outliers, choose row activation count, and program adaptive thresholds.
Training layerQuantization-aware training includes actual clipping, ADC codebook, saturation, offset, and output noise.
TradeoffHigh resolution costs area and energy; low resolution costs accuracy; adaptive flash-like ADCs can scale exponentially in threshold cells.
Large ideal crossbars become nonuniform physical networks
Hardware layerSmaller subarrays, access devices, stronger drivers, local ADCs, hierarchical routing, local SRAM, and balanced tile interfaces.
Compiler layerIR-drop-aware placement, physical row/column tiling, partial-sum planning, utilization-aware packing, replication, and communication scheduling.
Model layerPrune unimportant inputs, exploit structured sparsity, and choose architectures whose shapes pack efficiently.
TradeoffMore tiles, converters, buffers, routing, partial sums, and data movement reduce peak density and TOPS/W.
A correct deployment can become incorrect with time and temperature
Hardware layerReference/bias rows, temperature sensors, stable operating ranges, refresh support, redundant state, and better retention devices.
Training and compilerDrift-aware noise models, time-corner training, guardbands, per-use calibration metadata, and refresh/reprogram policy in the artifact.
RuntimeStore per-chip scale/offset and age, run health vectors, recalibrate, selectively refresh, fall back, and record every state transition.
TradeoffCalibration data, test time, downtime, maintenance energy, write endurance, and fleet-management complexity.
An analog MVM tile is not a complete NPU
Hardware layerDigital processing units, SRAM buffers, NoC, DMA, reductions, activation units, control processors, queues, trace, and reset.
Compiler layerCapability partitioning, analog/digital placement, fusion, scheduling, memory planning, format conversion, fallback, and a versioned executable artifact.
Runtime layerProgramming, calibration, queues, synchronization, telemetry, device-specific state, recovery, and compatibility negotiation.
TradeoffReal system efficiency must count auxiliary compute, data movement, utilization, programming, calibration, host work, and idle power.
Hardware solution hierarchy
Fix physical errors locally, then expose the residual error as a contract
Software solution stack
Make measured analog behavior a first-class compilation input
A normal NPU stack assumes deterministic instructions. An Analog CIM stack also consumes a target profile, nonideality model, per-chip state, and declared numerical tolerance.
Implementation boundary: this page explains why each hardware/software mechanism is needed. The Analog CIM SDK and compiler guide specifies the concrete libraries, calibration artifacts, C ABI, queues and events, MLIR passes, artifact schema, simulator/HAL backends, framework adapters, and first runnable MatMul slice.
Training and model preparation
- Start from a quantized digital baseline so analog loss is not confused with quantization loss.
- Inject measured weight, input, output, ADC, drift, and PVT distributions at the correct graph locations.
- Search the noise scale instead of assuming more noise always improves robustness.
- Use per-channel scaling, clipping, outlier splitting, distillation, and sensitivity analysis.
- Reserve chip-in-loop tuning for residual behavior the simulator cannot model accurately.
Compiler and optimizer
- Legalize only operators whose numeric and physical contracts the target can satisfy.
- Partition sensitive layers or kernels to SRAM/digital units and account for conversion overhead.
- Lower logical tensors into signed cells, bit slices, physical arrays, converter modes, routes, and partial sums.
- Use defect-, IR-drop-, saturation-, endurance-, and calibration-aware placement and scheduling.
- Emit a reproducible report explaining every fallback and predicted error contribution.
Runtime, firmware, and driver
- Discover device revision, array health, fault map, calibration age, firmware ABI, and precision modes.
- Program weights transactionally, then select cell-wise write-verify or random-probe MVM optimization from the target capability and deployment budget.
- Record programming loss, iteration count, pulse count, endurance use, and the final measured operator state.
- Store per-chip scale, offset, fault, temperature, age, and refresh data separately from portable model content.
- Monitor saturation, read variance, temperature, drift, timeouts, and device loss during execution.
- Support recalibration, selective refresh, remapping, digital fallback, rollback, quarantine, and replacement devices.
Simulator and validation
- Maintain FP32, digital-quantized, ideal-array, nonideality, cycle-model, RTL, and silicon references.
- Use measured distributions and preserve correlation IDs, model/artifact hashes, calibration version, and device state.
- Report first divergent layer, error distributions, tails, saturation, and task accuracy instead of one average MVM error.
- Correlate latency, energy, utilization, converter activity, movement, programming, calibration, and fallback.
- Qualify across chips, process, voltage, temperature, aging, faults, workloads, and time.
The June 2026 Nature Electronics result
"Fault-free" changes representation, not the laws of analog hardware
What the paper convincingly solves
- A target matrix can be factored into two adjustable matrices that route around severe stuck-device maps.
- The representation can eliminate conventional differential pairs and improve density for tested matrices.
- Gradient-based optimization can incorporate circuit/device constraints before programming.
- Measured DFT and wireless demonstrations show that the static-fault technique is real.
What remains unsolved
- Random read noise, ADC/DAC error, input-dependent nonlinearity, IR drop, coupling, temperature, and drift.
- End-to-end DNN accuracy, unsupported operators, model partitioning, scheduling, runtime, and field maintenance.
- The cost of the second MVM, analog bridge, compensation layers, calibration, and intermediate dynamic range for every workload.
- Population-level yield, long-term retention, endurance, and production qualification.
Compiler implication: treat matrix factorization as an optional physical-lowering strategy. It consumes a measured fault map and emits two array programs plus bridge/compensation configuration. The cost model must compare it with spares, remapping, differential encoding, retraining, digital fallback, and replacing the device. The method is valuable precisely because its claim is narrower than "analog is exact."
Solution selection matrix
Choose mitigations by error type, not by fashion
| Observed failure | First hardware response | First software response | Escalation |
|---|---|---|---|
| Random programming spread | Closed-loop write-verify, random-probe MVM support, and a stable conductance range. | Function-level programming optimization plus HWA training. | Multi-device expansion, remap, or digital placement. |
| Many stuck devices | Characterize fault map; spares where cheap. | Defect-aware placement or adaptive matrix factorization. | Reject/quarantine array when extra MVM stages lose value. |
| ADC saturation or code waste | Gain/offset control, precision modes, adaptive thresholds. | Representative calibration, per-layer range, clipping, outlier split. | More phases/bits or move the region to digital compute. |
| Read noise and nonlinear error | Linear read region, better sensing, differential/AB, references. | Measured-noise HWA training and sensitivity routing. | Average, expand weights, chip-in-loop tune, or fall back. |
| IR drop and position bias | Smaller arrays, access devices, stronger/local periphery. | IR-aware mapping, tiling, partial-sum and route planning. | Reduce active rows or redesign the tile. |
| Drift over time | Reference rows, sensors, refresh/reprogram capability. | Drift-aware training, calibration metadata, guardbands. | Recalibrate, selectively refresh, remap, or replace. |
| Sensitive model region | Provide SRAM/digital units and clean conversion paths. | Layer/kernel sensitivity partition and mixed precision. | Change model architecture or reject target deployment. |
| Poor application efficiency | Local SRAM, DPU, NoC, overlap, counters, power control. | Fusion, packing, scheduling, memory planning, pipeline balancing. | Redesign dataflow; peak macro TOPS/W is not the product metric. |
Implementation contracts
Six artifacts make the co-design reproducible
Evidence ladder
Do not let a component result silently become a product claim
The adaptive ADC paper contains measured memristor devices and converter characterization, then model and system evaluation under measured variation. The HWA training paper is a broad simulation study. NeuRRAM reports complete hardware-measured datasets. ALBERT maps the fully connected weights to hardware but keeps attention and activation work in software. These are all useful results, but they occupy different rungs.
Study and portfolio labs
Turn the papers into engineering evidence
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Primary sources