US 12,586,636 B2 was granted on March 24, 2026. Its independent claims cover a particular hybrid line-significance and reconstruction architecture, not every form of bit-sliced CIM.
Patent deep read | research snapshot 2026-07-11
iHW's ACiM Patent Stack: What It Solves and What It Does Not
Intelligent HW's granted hybrid-computing patent attacks a real analog-memory problem: asking one physical cell to hold many precise conductance levels. Its answer is to build one logical weight from simpler digits, accumulate each positional slice in analog, then reconstruct precision digitally. Later applications add adaptive converter range, grouped quantization, and signed-current cancellation. Together they form a credible accuracy architecture, but they are not public proof that end-to-end analog error is solved.
Core US grantUS 12,586,636 B2, granted March 24, 2026
Main mechanismPositional digit slices plus digital reconstruction
Supporting layerAdaptive ADC, grouped scales, signed cancellation
Research verdictPartial mitigation; system-level proof remains open
Evidence boundary
A real granted architecture claim is not the same as a verified product result
Best-supported conclusion: iHW has a technically meaningful way to avoid depending on a single highly precise multilevel memory cell. The granted architecture can make logical weight encoding more controllable, while the newer applications address converter range, quantization range, and signed-weight peripheral cost. Public records still do not establish full-model accuracy, yield, energy, latency, or lifetime behavior across production chips.
An iHW recruiting page claims a world-first 8-bit-weight ACiM silicon verification and MobileNet demonstration. No public independent benchmark methodology accompanies that statement.
The patent record does not report complete datasets, chip populations, PVT corners, aging, yield, full-chip energy, or end-to-end latency.
Patent or official record
Company disclosure
Engineering interpretation
Read "8-bit" carefully
In the core patent, an 8-bit logical weight may be reconstructed from eight robust binary slices or from fewer multi-bit slices. It does not require one physical cell to reproduce 256 ideal conductance states. Logical precision, converter precision, analog effective precision, and end-task accuracy are four different quantities and should never be reported as if they were interchangeable.
Patent landscape
One granted representation architecture plus a surrounding accuracy stack
Status below is the US public-record status at this research snapshot. A pending application describes a proposed invention; it must not be presented as a granted right or as proof that the mechanism ships in silicon.
| Document | Status | Problem addressed | Proposed mechanism | Evidence limit |
|---|---|---|---|---|
| US 12,586,636 B2Hybrid computing method and neuromorphic system | Granted 2026-03-24 | Multilevel-cell nonlinearity, poor repeatability, and unary-cell density cost | Represent a logical weight as positional digits; perform analog accumulation per slice; digitally shift, scale, and add | Architecture claims, not a public full-chip benchmark |
| US 2025/0348726 A1High-accuracy analog computing | Pending application | ADC saturation or wasted resolution across wide output-current ranges | Classify current magnitude and select a matching I-V conversion or ADC range | No public product implementation or end-to-end cost result |
| US 2025/0348716 A1Weight quantization for analog computing | Pending application | Accuracy loss when one quantization scale covers a layer with uneven channel ranges | Use multiple quantization groups and dequantize each group with its own scale | Compiler policy and measured model benefit are not public |
| US 2026/0023963 A1Negative-weight analog computing unit | Pending application | Peripheral duplication for positive and negative weight paths | Alternate positive and negative split-gate cells on one bitline so currents cancel before conversion | Claims fewer ADCs; cancellation accuracy and residual range remain design risks |
| US 2026/0024581 A1Negative-weight array arrangement | Pending application | ADC count and positive/negative read overhead | Rearrange control-line directions and alternate paired read modes | One-quarter-ADC claim is an application claim, not a measured product result |
| US 12,268,104 B2Chalcogenide memory-cell composition and operation | Granted 2025-04-01 | Threshold drift, read window, stable composition, and manufacturability | Material composition plus initialization and read techniques | A separate device path; it does not prove the flash ACiM product uses this material |
Core patent mechanism
Trade one fragile analog level for several simpler positional digits
The architecture is hybrid by construction. Memory cells provide parallel analog multiply-accumulate work; converters and digital logic recover the significance of each slice.
One cell, many conductance levels
A dense direct mapping asks each device to separate many analog states despite program variation, read noise, nonlinear response, drift, temperature, aging, and process spread. More nominal bits do not automatically produce the same number of effective bits.
Several cells or lines, fewer states each
Each slice can use a small, robust state set, including on/off. Positional significance carries the high precision, and deterministic digital arithmetic reconstructs the logical value after conversion.
W[i,j] = sum_k d[i,j,k] * R[k]
I[k,j] ~= alpha * sum_i X[i] * d[i,j,k]
Y[j] = sum_k R[k] * ADC(I[k,j])
d[i,j,k] digit stored in a physical memory state
R[k] positional significance, such as 1, 2, 4, 8 ...
I[k,j] analog output current for significance slice kWorked example from the disclosed idea
If three digit-line currents convert to 9, 1, and 3, and their positional weights are 1, 2, and 4,
digital reconstruction produces 9 x 1 + 1 x 2 + 3 x 4 = 23. The analog array need not create
one current that directly encodes 23 with a single precise cell state.
Reliability policy
Mixed radix lets significance determine how much cell reliability to buy
The cost does not disappear. More slices can require more cells, output lines, ADC phases, routing, input cycles, digital shift-add work, and calibration metadata. Fewer slices save area and cycles but reintroduce multilevel-cell variability. The engineering problem becomes an explicit accuracy-area-energy-latency tradeoff.
Supporting inventions
The later applications target costs left around digit-sliced representation
Adaptive output and ADC range
A multiplexer selects an output current, a grading step estimates its magnitude, and the circuit selects a matching I-V resistance/capacitance, ADC reference, or oscillator capacitance.
Benefit: reduce saturation on large sums and avoid wasting ADC codes on small sums.
Moved cost: grading, references, calibration, extra control, and possible multiplexing latency.
Grouped weight quantization
A layer is split into several quantization groups, often aligned with output channels or output-line groups. Each group receives its own scale for quantization and dequantization.
Benefit: reduce error caused by one outlier-dominated scale covering a heterogeneous layer.
Moved cost: more scale metadata, grouping constraints, compiler decisions, and digital dequantization.
Signed-current cancellation
Positive and negative split-gate flash cells alternate on a shared bitline so the ADC measures a residual current rather than two independently converted sums. A related arrangement changes control-line direction and paired read modes.
Benefit claimed: reduce the ADC count to one-half or one-quarter of a prior separate-path design.
Moved cost: device matching, bias control, cancellation accuracy, small-residual resolution, and common-mode headroom.
Chalcogenide drift and read window
A separate patent addresses composition, initialization, and read behavior for a chalcogenide memory cell, including threshold drift and stable operation.
Benefit: improve a device-level memory path that could support analog computation.
Boundary: do not infer that the disclosed flash ACiM product uses this separate material system.
Accuracy budget
Trace every error source instead of asking whether "analog accuracy" is solved
| Error or cost source | iHW mechanism that helps | What remains | Where the cost moves |
|---|---|---|---|
| Many levels in one cell | Positional digit slicing permits fewer robust states per cell. | Each state still has program and read variation. | Cells, lines, ADC phases, or cycles plus shift-add logic. |
| High-significance error | Mixed-radix mapping can assign more reliable cells to larger digits. | An MSB error is multiplied by its significance. | Area or density is spent on robust high-order storage. |
| ADC range and resolution | Adaptive output-range application selects conversion settings by current grade. | Offset, gain, noise, nonlinearity, reference drift, and grading error. | Range sensing, references, calibration, multiplexing, and control. |
| Outlier-dominated quantization | Group-specific scales narrow the represented range. | Group boundaries, scale quantization, activation error, and model sensitivity. | Metadata, compiler search, and digital dequantization. |
| Signed weights | Differential reconstruction or pre-ADC current cancellation. | Mismatch and residual-current precision. | Matched devices, bias circuitry, and common-mode control. |
| Array parasitics | No complete solution established by the reviewed claims. | IR drop, line resistance, sneak paths, coupling, and location-dependent gain. | Smaller arrays, models, compensation, remapping, or extra conversion. |
| PVT and lifetime | Device patent addresses one drift path; calibration may compensate some effects. | Temperature, voltage, process spread, retention, endurance, aging, and read disturb. | Characterization, sensors, refresh, redundancy, field policy, and yield loss. |
| Whole-model execution | Digital reconstruction makes the matrix primitive usable by a conventional stack. | Activations, normalization, reductions, attention, routing, fallback, and communication. | Digital engines, SRAM, interconnect, firmware, compiler, and runtime. |
Accuracy is a budget, not a bit label: task error combines model quantization, cell state, input encoding, array transfer, conversion, digital accumulation, calibration age, and unsupported-operation handling. A defensible result reports each contribution and the hardware or software paid to reduce it.
Patent-to-software bridge
Turn each claimed mechanism into a compiler or runtime contract
This section traces the patent mechanisms into required software semantics; it is not a disclosure of iHW's implementation. The companion SDK guide defines the module boundaries, public API, artifact schema, simulator/HAL contract, first vertical slice, and CI plan needed to turn those requirements into code.
Continue with the build specification: Analog CIM SDK and Compiler: From Model to Running Code separates model calibration, target characterization, and device state, then follows one ONNX MatMul through compilation, packaging, simulation, and execution.
Four compile inputs define one reproducible deployment
A model file alone is insufficient because two chips of the same product can have different usable arrays, calibration state, and numerical limits.
graph + tensorsOperations, shapes, dynamic dimensions, dtypes, constants, control flow, ranges, and reference outputs.quality + service goalsAccuracy floor, latency percentile, power mode, batch, analog coverage target, fallback allowance, and model lifetime.device + ABIArray geometry, memory, NoC, digital engines, ADC sharing, pulse modes, firmware features, and command limits.measured transfer modelPer-array gain, offset, noise, saturation, IR-drop model, weak cells, PVT curves, drift, and calibration validity.Multi-level IR
Keep graph meaning separate from physical array decisions
A staged MLIR design allows target-neutral optimization to finish before hardware commitments become explicit. Each lowering boundary should make previously implicit numerical behavior visible and verifiable.
| IR level | What it represents | Required ACiM information | Examples of legal transformations |
|---|---|---|---|
| Framework IR | PyTorch export, ONNX, StableHLO, or another frontend graph | Framework semantics, symbolic shapes, constants, state, and reference numerics | Constant folding, shape inference, canonicalization, and framework decomposition |
| ACiM graph IR | Target-independent tensor operations plus support and sensitivity annotations | Candidate precision, error budget, legal fallback, calibration dataset identity, and fusion barriers | Operator decomposition, algebraic simplification, fusion, layout-neutral partitioning, and quantization preparation |
| ACiM tensor IR | Analog and digital partitions with explicit tensor layouts and scale domains | Group scales, clipping, signed representation, partial-sum format, residency, and conversion boundaries | Scale propagation, requantization removal, channel grouping, tiling, sharding, and buffer reuse |
| ACiM physical IR | Logical tensors placed onto physical cells, lines, converters, and digital units | Digit/radix slices, positive and negative paths, fault remap, ADC grade, input pulses, and calibration key | Array packing, slice co-location, spare substitution, ADC assignment, phase merging, and digital residual placement |
| Command IR | Firmware-visible queues, dependencies, synchronization, and state transitions | Program/verify, MVM phase, convert, shift-add, DMA, barrier, health check, refresh, and fallback commands | Command fusion, asynchronous overlap, double buffering, converter pipelining, and event elimination |
| Executable artifact | Versioned binary delivered to the runtime | Target contract, cell image, command streams, buffers, calibration schema, debug maps, and provenance | Serialization, signing, compatibility validation, caching, and deterministic rebuild comparison |
Pass pipeline
The backend should fail early, then lower in measurable steps
| Order | Compiler pass | Main decision | Emitted evidence |
|---|---|---|---|
| 1 | Import and semantic normalization | Resolve framework-specific operators into a stable supported operation set without changing model meaning. | Importer diagnostics, normalized graph, unsupported semantic list, and reference tensor names |
| 2 | Shape, range, and sensitivity analysis | Infer symbolic shapes and collect activation ranges, outliers, per-layer error sensitivity, and representative data coverage. | Range histograms, sensitivity score, calibration dataset hash, and dynamic-shape constraints |
| 3 | Capability and legality analysis | Enumerate analog, digital, and host implementations for every operation and reject impossible tensor shapes or modes. | Support report with reason codes and the legal implementation set per operation |
| 4 | Quantization and scale-domain planning | Select group boundaries, weight/activation precision, clipping, rounding, accumulator width, and dequantization placement. | Quantization manifest and software-equivalent accuracy result |
| 5 | Analog/digital partitioning | Choose ACiM regions only when saved movement and MVM time exceed conversion, correction, and boundary costs. | Partition graph, analog coverage, fallback edges, and boundary tensor costs |
| 6 | Weight decomposition | Convert each logical weight into radix digits, significance slices, and signed paths under reliability constraints. | Logical-to-physical weight map with reconstruction equation |
| 7 | Array placement and fault remap | Pack slices into arrays while respecting geometry, weak-cell maps, current limits, locality, and spare capacity. | Array occupancy, rejected capacity, remap table, and utilization report |
| 8 | ADC and phase planning | Select range grade, converter sharing, one- or multi-phase reads, repeated sensitive reads, and saturation guard bands. | Per-output conversion plan, predicted ENOB/error, phases, and saturation risk |
| 9 | Memory and schedule planning | Allocate SRAM and host buffers; overlap input encoding, MVM, conversion, shift-add, digital work, DMA, and NoC traffic. | Static arena, queue schedule, lifetime graph, bandwidth estimate, and critical path |
| 10 | Calibration binding | Bind placement to a compatible calibration class or a specific device calibration without embedding stale measurements blindly. | Calibration requirements, accepted versions, temperature window, and expiry policy |
| 11 | Command lowering and packaging | Generate firmware descriptors, program images, digital kernels, debug correlation IDs, and ABI-versioned metadata. | Inspectable artifact plus deterministic build manifest |
| 12 | Differential verification | Compare framework, quantized, physical-simulator, RTL/model, and silicon checkpoints at graph boundaries. | Accuracy deltas, first divergent operation, tolerance decision, and release gate result |
Candidate search
Optimize latency and energy under an explicit error constraint
minimize candidate_cost =
latency_weight * predicted_latency
+ energy_weight * predicted_energy
+ boundary_weight * analog_digital_transfer
+ programming_weight * weight_program_cost
+ wear_weight * expected_refresh_and_endurance_cost
+ risk_weight * numerical_uncertainty
subject to:
predicted_accuracy_loss <= deployment.error_budget
array_current <= adc_range_limit
buffers <= available_sram
cells + spares <= usable_array_capacity
phases <= latency_policy.max_phases
calibration is compatible and not expired
firmware_abi supports every emitted commandT = phases x read + ADC + digital + NoCUse measured queue overlap and contention, not a sum of isolated peak timings.E = input + array + ADC + SRAM + NoCInclude calibration, refresh, fallback, idle power, and converter under-utilization.R = quant + cell + wire + ADC + driftCombine characterized distributions and model sensitivity rather than nominal bit counts.C = useful analog work / total workReport actual model coverage after fallback and boundary operations.Physical operation contract
One MVM operation needs more attributes than shape and dtype
%result = acim.mvm %activation, %weight_image {
logical_type = i8,
activation_mode = #acim.pulse<bits = 4, phases = 2>,
weight_digits = [#acim.digit<radix = 4, significance = 1>,
#acim.digit<radix = 2, significance = 4>],
signed_mapping = #acim.differential<positive = 12, negative = 13>,
placement = #acim.array<tile = [3, 2], rows = 0:128, cols = 0:64>,
adc = #acim.adc<grade = 2, bits = 6, saturation_guard = 0.12>,
accumulator = #acim.accum<i24, round = nearest_even, saturate = true>,
calibration_key = "family7/revB/tile3x2/class4",
fallback = #acim.digital<engine = vector1, trigger = saturation>
} : tensor<1x128xi4> -> tensor<1x64xi24>Tool suite
The compiler is one tool inside a closed measurement loop
| Tool | Purpose | Required output |
|---|---|---|
acim-import | Import and normalize ONNX, StableHLO, or framework export while retaining source locations. | Graph IR, support diagnostics, shape constraints, and reference tensor manifest |
acim-characterize | Turn wafer, production, and lab measurements into signed target profiles. | Versioned per-family and per-device transfer models, PVT curves, fault maps, and confidence intervals |
acim-calibrate | Collect representative activation ranges and optionally run hardware-in-loop measurements. | Dataset hash, ranges, clipping choices, sensitivity metrics, and calibration provenance |
acim-opt | Run IR verification, quantization, partitioning, mapping, scheduling, and command lowering passes. | Intermediate IR dumps, pass statistics, candidate comparison, and selected plan |
acim-sim | Execute functional, statistical analog, cycle, and command-level models through one API. | Outputs, error distributions, saturation events, cycles, bytes, and model-version identity |
acim-pack | Serialize cell images, commands, metadata, digital kernels, and debug maps. | Signed and inspectable executable artifact with target and ABI compatibility fields |
acim-run | Load, validate, program, execute, and collect structured runtime results. | Result tensors, health state, calibration ID, timing, faults, and recovery actions |
acim-prof | Correlate graph operations with arrays, converter phases, queues, SRAM, NoC, and digital fallback. | Timeline, utilization, bandwidth, phase count, converter occupancy, and critical path |
acim-debug | Stop at operation boundaries and compare logical, quantized, simulated, and measured tensors. | First divergence, per-slice ADC values, reconstruction trace, and source-level location |
Validation ladder
One operation should run through every model with the same artifact semantics
Capture deterministic tensors and source locations before quantization.
Prove scales, clipping, rounding, saturation, and accumulator behavior in software.
Inject measured cell, wire, converter, temperature, and drift distributions.
Validate resource conflicts, phases, buffers, dependencies, timeout, and recovery.
Correlate command fields, fixed-point arithmetic, interrupts, and firmware state.
Compare per-line ADC values and reconstructed outputs against characterization.
Measure contention, thermal gradients, cross-array spread, fallback, and PVT tails.
Require full-dataset accuracy, latency percentiles, energy, coverage, and lifetime policy.
| Software layer | Required ACiM contract | Failure if hidden |
|---|---|---|
| Quantizer | Group boundaries, scale format, clipping, rounding, signed policy, and sensitivity budget | Software-equivalent accuracy does not match mapped hardware. |
| Compiler IR | Logical weight digits, radix/significance, positive/negative paths, converter mode, calibration dependency | Optimization passes reorder or fuse operations illegally. |
| Mapper and scheduler | Array geometry, line limits, ADC sharing, pulse cycles, fault maps, digital engines, and synchronization | Latency, energy, and numerical behavior become unpredictable. |
| Artifact packager | Target/ABI, cell programming image, scales, range grades, commands, buffer plan, calibration version, provenance | A binary blob cannot be validated, reproduced, cached, or upgraded safely. |
| Runtime and firmware | Program/verify lifecycle, queue semantics, saturation and drift counters, refresh, reset, rollback, and fallback | Lab accuracy cannot survive deployment or field aging. |
| Debugger and profiler | Per-line current, ADC code, positional contribution, reconstructed output, timing, saturation, and calibration ID | The first divergent layer and physical cause remain invisible. |
acim_artifact:
target: {device, revision, firmware_abi, compiler_version}
graph: {partitions, tensor_contracts, fallback_edges, source_debug_map}
weights: {cell_image, digit_radix, significance, signed_mapping, fault_remap}
numerics: {group_scales, clipping, adc_ranges, accumulators, error_budget}
schedule: {program_steps, mvm_slices, convert, shift_add, dma, events}
memory: {host_buffers, device_sram, constants, mutable_state}
calibration: {schema, accepted_classes, version, temperature_window, expiry_policy}
recovery: {saturation_action, weak_array_action, timeout_action, digital_fallback}
provenance: {model_hash, dataset_id, target_profile_hash, options, build_id}Tenstorrent reuse boundary
Reuse compiler engineering patterns; replace the hardware meaning
Frontend and infrastructure
Model import, MLIR pass organization, differential tests, artifact versioning, runtime API patterns, CI, profiling UX, and model-corpus practices can shorten development after license and dependency review.
Tensix execution assumptions
Tile grids, circular buffers, NoC transfers, digital kernel scheduling, TT-Metal device semantics, UMD, and KMD do not describe cells, digit lines, ADC ranges, calibration, drift, or program/verify behavior.
ACiM operations
A practical backend needs concepts such as program_array, mvm_slice, adc_read, shift_accumulate, calibrate, refresh, and digital fallback.
| Tenstorrent component or pattern | Initial decision | ACiM use | Required change |
|---|---|---|---|
| MLIR infrastructure and TTIR layering | Adapt | Preserve a high-level tensor IR, source locations, pass pipelines, verification, and dialect conversion structure. | Define target-neutral ACiM graph semantics rather than importing TTNN layouts or Tensix execution meaning. |
| TTNN optimizer pattern | Adapt | Generate legal per-operation candidates and select layouts/configurations with an operation model. | Add precision, ADC, characterization, phase, wear, fault-map, calibration, and fallback dimensions to the search. |
| System descriptor and device attributes | Adapt | Cross-compile against a captured physical target and validate executable compatibility at runtime. | Describe arrays, converters, pulse modes, digital companions, calibration classes, firmware commands, and health capabilities. |
FlatBuffer and ttrt pattern | Adapt | Use versioned, inspectable artifacts plus read, run, check, perf, and debug tools. | Serialize cell images, reconstruction plans, calibration requirements, recovery policy, and physical debug correlation. |
| TT-Explorer workflow | Adapt | Visualize graphs, compiler overrides, execution traces, memory, and operation results. | Add array maps, digit slices, ADC phases, error budget, saturation, drift, faults, and analog coverage views. |
| TTNN, TTMetal, and TTKernel dialect semantics | Study only | Learn explicit layouts, dataflow, queues, kernels, synchronization, and performance engineering. | Replace Tensix-specific operations with program, pulse, MVM, convert, reconstruct, calibrate, refresh, and fallback operations. |
| Metalium device runtime, UMD, and KMD | Replace | Reuse only proven target-neutral utilities after license and dependency review. | Implement the ACiM command ABI, DMA, interrupts, isolation, power, reset, programming, health, and recovery stack. |
| IBM AIHWKit concepts | Reference | Model device variation, ADC/DAC bounds, noise, hardware-aware training, input scaling, and analog inference. | Calibrate models to iHW silicon and connect simulator parameters to compiler IR, target profiles, and release thresholds. |
acim-toolchain/
frontend/ ONNX, StableHLO, and framework import adapters
dialect/ Graph, tensor, physical, and command IR definitions
analysis/ Shape, range, sensitivity, legality, and error propagation
optimizer/ Candidate generation, cost model, partition, map, schedule
target/ System descriptors and characterization database schemas
codegen/ Firmware commands, digital kernels, and artifact serialization
simulator/ Functional, statistical analog, cycle, and command models
runtime/ Session, buffers, queues, programming, health, and recovery
firmware/ Descriptor validation, scheduling, telemetry, reset, and refresh
tools/ Import, characterize, calibrate, inspect, run, profile, and debug
tests/ IR, golden, differential, silicon, PVT, aging, and model suitesIf Tenstorrent built this type of ACiM device, its existing discipline around explicit dataflow, compilation, testing, and observability would still be valuable. The central optimization target would change from mainly moving tiles between DRAM, SRAM, and core grids to jointly controlling analog error, conversion, slicing, programming, calibration, and digital escape paths. See the full reuse decision guide.
Paper and patent review checklist
Ten questions answered from the public iHW record
"Not disclosed" is an answer. It prevents an architecture document or company statement from quietly becoming evidence for a stronger accuracy or efficiency claim.
| Review question | Answer for the reviewed iHW record | Confidence |
|---|---|---|
| 1. Fabricated silicon, device traces, or simulation? | The patents describe architectures. A company recruiting page claims 8-bit-weight ACiM silicon verification and a MobileNet demo, but no independent silicon report or raw trace set was found. | Mixed evidence |
| 2. Did the complete validation dataset run through hardware? | Not disclosed. "MobileNet demo" does not establish dataset coverage, which layers ran in analog, sample count, or repeated-chip testing. | Open |
| 3. What accuracy baseline was used? | Not disclosed in the reviewed public claim. Require FP32, production digital quantized, software-equivalent ACiM, and measured silicon results on the same model and data. | Open |
| 4. Which work remained off-chip or digital? | The patent explains matrix representation and reconstruction, not complete-network placement. Activation, normalization, pooling, attention, routing, partial sums, and host work are not quantified. | Open |
| 5. How much retraining, calibration, redundancy, or refresh? | Digit slicing, range selection, and grouped quantization imply software and calibration support, but the training recipe, chip-in-loop burden, spare capacity, refresh interval, and field policy are not public. | Open |
| 6. Are energy and latency end to end? | No public end-to-end result was identified for this patent stack. Count programming, input encoding, all ADC phases, digital reconstruction, companion operations, SRAM/interconnect, host traffic, calibration, and idle power. | Open |
| 7. Accuracy across chips, PVT, defects, and time? | No public population distribution, process-corner sweep, voltage/temperature sweep, defect policy, retention curve, endurance result, or calibration-age curve was identified. | Open |
| 8. Does mitigation preserve density and efficiency? | Not automatically. Digit slices, adaptive ranges, group scales, matched signed paths, and digital recombination can move cost into cells, lines, converters, cycles, metadata, calibration, or digital logic. | Conditional |
| 9. Inference, training, or both? | The reviewed architecture is most directly supported as an inference-weight path. Static inference weights avoid the update-linearity and endurance burden of on-chip training; do not treat the patents as training proof. | Inference focus |
| 10. Can it scale to the target model? | Not established for large LLM parameter counts, irregular tensor shapes, long context, KV-cache traffic, attention, communication, or multi-chip execution. A 4-bit LLM weight format alone does not answer these system questions. | Open |
Interview and technical due diligence
Questions that turn patent language into a product contract
Logical weights after reconstruction, cell states, ADC output, accumulator, software-equivalent model, or measured effective precision?
Report cells, lines, ADCs, read phases, input pulses, shift-add operations, and spare capacity.
Separate the granted core patent from pending ADC, quantization, and signed-weight applications and identify the implemented revision.
Compare FP32, digital INT8/INT4, software ACiM, measured raw ACiM, calibrated ACiM, and hybrid fallback.
Ask for lot count, chip count, weak arrays, rejected devices, remapping rate, yield, and worst-case accuracy.
Define factory, boot, thermal, periodic, workload, aging, refresh, rollback, and field-update responsibilities.
Quantify analog coverage, unsupported operators, transfer boundaries, digital correction, SRAM, DRAM, and host work.
Inspect importer, IR, compiler, simulator, artifact, runtime, firmware, driver, profiler, debugger, and version negotiation.
Final assessment
Technically plausible, complementary, and still evidence-limited
The core iHW grant solves a narrower and more defensible problem than "analog accuracy": it reduces reliance on fragile high-level-count cells by moving precision into positional representation and digital reconstruction. The pending ADC, grouped-quantization, and signed-current ideas address important adjacent costs. This is a coherent hardware/software strategy. It becomes a product-level accuracy solution only when the company shows complete models, analog coverage, correction cost, chip distributions, PVT and lifetime behavior, yield, and end-to-end energy and latency against clear digital baselines.
Sources