Mythic & Analog Compute-in-Memory Architecture

Terminology

AiCM, AIMC, AiMC, and analog CIM

The research literature most often says analog in-memory computing (AIMC or AiMC). Analog compute-in-memory (analog CIM or ACIM) expresses the same central idea. This study treats AiCM as the user's name for that family. It is different from digital CIM, which performs exact bit operations inside or beside a memory array.

The physical primitive

One matrix-vector multiply in five steps

The ideal equation is compact. Every production challenge enters through the assumptions hidden underneath it.

Digital activation x_i Quantized input value

Input encoding V_i ∝ x_i Voltage, pulse, or duration

Cell multiply I_ij ≈ V_iG_ij Ohm's law in the read region

Column sum I_j ≈ Σ_iI_ij Current or charge accumulation

Digital output ŷ_j = ADC(I_j) Quantized result plus scaling

Ideal assumption

Cells are linear and independent

Real I-V curves, source resistance, wire drop, coupling, and sneak paths make a large array input dependent.

Ideal assumption

Weights stay where programmed

Programming spread, defects, relaxation, drift, temperature, and aging change the effective conductance.

Ideal assumption

Readout preserves information

ADC range, offset, noise, resolution, and saturation place a ceiling on useful end-to-end precision.

From tensor operation to physical math

A framework MatMul becomes repeated analog matrix-vector operations

Software usually presents a matrix-matrix operation. A conductance array naturally evaluates one input vector against a resident weight matrix. Batch rows, oversized dimensions, signs, and additional bits are handled through repeated firings, parallel arrays, and digital reconstruction.

GEMM: matrix by matrix MVM: one vector by resident weights MAC: one product added to a sum Row driver: presents an activation to array rows Column readout: senses a dot-product result Partial sum: one contribution to a larger output Sequencer: hardware that times drivers, sampling, and conversion

Short answer: where does the MatMul happen?

For C[B,N] = A[B,K] x W[K,N], the compiler places blocks of W into conductance arrays. For each batch row A[b,:], input circuitry drives a vector onto array rows. Each memory cell performs the physical product V_iG_ij; each column wire and sensing circuit accumulates those products; the ADC creates digital partial results; and nearby digital logic subtracts signed paths, combines bit planes and array partitions, applies scale and bias, and stores or routes C[b,:]. The RISC-V controller schedules this work; it does not execute the bulk analog MACs.

InputA[B,K]B activation vectors, each with K elements

Resident weightsW[K,N]K physical rows by N logical outputs before tiling

Array primitivea_b[K] x W[K,N]One logical MVM per batch row, possibly split across arrays and bit phases

ResultC[B,N]Stack or stream the reconstructed N-element output vectors

Layout convention: these diagrams use the mathematical form A[B,K] x W[K,N]. A framework may store a linear-layer weight as W[N,K] and request an implicit transpose. The importer and compiler must normalize that storage convention before physical mapping.

Deployment or model change Weight path is rare and stateful

Quantized weights→Physical mapping→Program + verify→Resident conductance handle

Programming may require write pulses, verify reads, remapping, and calibration. It is not repeated for every inference.

Every inference or token Activation path is streamed

Input tensor→DMA / NoC→Local SRAM→Array + ADC→Digital result

Activations, partial sums, and outputs move. Correct mapping tries to keep the much larger weight population stationary.

One ACiM MatMul execution path The lanes distinguish orchestration, movement, physical computation, and digital reconstruction.

Control Transfer / storage Analog math Digital math Persistent state

Control

Compiled artifactPlacement, buffers, phases, routes, scales

Host runtimeBind input/output and enqueue graph

Tile controllerValidate state and issue tile commands

ACE sequencerGenerate cycle-level drive, sample, ADC timing

Movement

Host / sensorProduce activation tensor

DMA or fabricTransfer aligned blocks

NoC routerDeliver to assigned tile

Local SRAMBuffer input and output blocks

Input registersFeed row-driver format

Output SRAMHold reconstructed tensor

NoC / DMARoute to next layer or host

Analog math

Input driveVoltage, pulse, duration, or digital approximation

Memory cellsI_ij ≈ V_iG_ij performs multiplication

Column networkI_j ≈ Σ_iI_ij performs accumulation

Sample / integrateCapture bounded analog result

ADC / comparatorConvert result to a digital code

Digital math

Signed combineSubtract positive and negative paths

Bit reconstructionShift and add input or weight slices

Partition reductionAdd partial vectors from K shards

EpilogueScale, zero point, bias, clamp, activation

State

ConductancesResident physical weights

CalibrationDriver, column, ADC, scale coefficients

Health mapDefects, remaps, drift, temperature epoch

Execution bindingValidated weight and profile handles

Where the parallel arithmetic physically occursA small logical 3-input by 3-output example

Driven rowOutput 0Output 1Output 2

x₀ → V₀V₀G₀₀V₀G₀₁V₀G₀₂

x₁ → V₁V₁G₁₀V₁G₁₁V₁G₁₂

x₂ → V₂V₂G₂₀V₂G₂₁V₂G₂₂

Column resultΣ_iV_iG_i0Σ_iV_iG_i1Σ_iV_iG_i2

Digital boundaryADC 0ADC 1ADC 2

MultiplyMemory cellThe programmed conductance interacts with the driven row signal. No instruction is issued for each individual multiply.

AccumulateColumn wire and sensing circuitCurrents or charge contributions combine by circuit behavior before conversion.

QuantizeADC or comparatorThe analog result becomes a bounded digital code and may require multiple conversion cycles.

ReconstructSIMD, DSP, or fixed digital logicSigned paths, bit planes, partitions, scale, bias, and activation become the final tensor value.

Signed weightsW ∝ G⁺ - G^-Many arrays cannot represent negative conductance. Positive and negative lines or an offset representation are measured separately and combined digitally.

Multi-bit activationx = Σ_p2^px^(p)A full DAC may present a multi-level signal, or several bit/pulse phases may be fired and shifted into alignment afterward.

Multi-cell or sliced weightW = Σ_s2^sW^(s)Several conductances or arrays can encode one logical weight; their ADC codes require weighted digital accumulation.

Oversized K dimensionC_n = Σ_kP_k,nEach K shard produces a partial output vector. A digital accumulator combines those vectors before the layer is complete.

Mythic evidence boundary: the public M1076 brief documents the ACE, RISC-V nano-processor, SIMD processor, SRAM, and NoC router, while the Hot Chips presentation documents flash-resistor MVM, digital input approximation, and ADC readout. Public material does not specify the internal ACE command registers, exact sequencer, firmware ABI, per-cycle schedule, or which digital block owns every reconstruction step. The diagrams above show the required architectural responsibilities and mark the most reasonable block ownership without presenting an undisclosed implementation as fact. M1076 brief | Hot Chips presentation

Control plane and data plane

Three control timescales turn one graph operation into array pulses

Software chooses what should run. Firmware coordinates when resources are ready. Dedicated hardware produces the precise electrical timing.

Compile timeGraph compilerChooses array tiles, signed/bit representation, K/N partitions, buffer addresses, routes, digital fallback, scales, and command templates.

Command timeRuntime and tile controllerValidate the executable and device state, bind tensor addresses, wait for dependencies, configure resources, start work, and report completion or faults.

Cycle timeACE-local hardware sequencerTimes row drive, settling, sample/integrate, ADC phases, register capture, and backpressure. Software should not toggle every switch directly.

Sequence for one already-programmed weight tileWeight programming and calibration happen before this steady-state path.

StepHost runtimeTile controllerDMA / NoC / SRAMACE + readoutSIMD / digital

1enqueue(program, input, output)

2Validate ABI, tensor bounds, resident weight handle, calibration and health epochs

3Issue input transfer and wait on producer eventMove activation block to local SRAM; publish input-ready credit

4Bind row/column ranges, precision mode, phase count, output slot, and start command

5Read input register or SRAM slice for the current phaseDrive rows; cells multiply; columns accumulate; sample or integrate

6Run ADC/comparator phases and latch digital column codes

7Subtract signed paths; shift/add slices; reduce K partitions; apply scale, bias, clamp, activation

8Wait for the final write or route barrier, then publish output-ready and release buffer creditsStore output in SRAM, route it to the next destination, and signal transfer completion

9Observe completion or continue the captured graphUpdate counters; report saturation, retry, timeout, or fault state

Component	Primary responsibility	Moves tensor data?	Performs math?	What must be explicit in software
Graph compiler	Convert graph semantics into array placement, schedule, buffers, routes, and a device artifact.	No runtime transfer	Constant folding and reference analysis only	Shapes, precision, tiling, partition reductions, capability and fallback decisions.
Host runtime / driver	Discover the device, load artifacts, bind buffers, enqueue work, synchronize, handle faults and reset.	Requests DMA; may copy at external boundaries	CPU fallback and preprocessing when assigned	Buffer lifetime, queues, events, timeout, ABI and device-state compatibility.
Tile RISC-V / controller	Sequence coarse tile operations, dependencies, descriptors, local resource setup, and completion.	Commands movers; may perform scalar loads/stores	Small scalar/control work, not the bulk MVM	Command format, synchronization, firmware ownership, counters, fault and recovery behavior.
DMA / NoC router	Transfer activations, partial sums, commands, and outputs between host, memory, and tiles.	Yes	No neural-network arithmetic	Address spaces, alignment, routes, bandwidth, multicast, ordering, barriers, and backpressure.
Local SRAM / registers	Hold activation blocks, output slots, descriptors, temporary partial sums, and digital state.	Storage endpoint	No	Bank ownership, capacity, lifetime, double buffering, layout, and producer/consumer credits.
ACE-local sequencer	Generate deterministic row-drive, settling, sensing, conversion, and capture timing.	Feeds local registers and readout	Controls the circuits that perform math	Precision modes, phase counts, resource hazards, timeout, saturation, retry and telemetry contract.
Conductance array	Store weights and evaluate many cell products and column sums in parallel.	Weights remain in place	Bulk analog multiply and accumulate	Array dimensions, conductance encoding, signed mapping, defects, operating range and nonideality model.
ADC / readout	Sense, integrate or compare column results and produce bounded digital codes.	Creates the analog-to-digital boundary	Quantization and sometimes threshold/nonlinearity	Sharing, range, resolution, latency, energy, calibration, saturation and output format.
SIMD / DSP / fixed digital logic	Reconstruct slices and partitions; execute supported vector epilogues and non-array operators.	Reads/writes local buffers	Digital accumulation and epilogue math	ISA or kernel API, accumulator width, rounding, saturation, fusion, and fallback cost.

Design rule: the control processor should issue compact work descriptors and handle exceptional control. A dedicated sequencer should own repetitive cycle-level analog timing. If firmware must micromanage every input phase, ADC lane, and transfer, controller utilization and NoC traffic can erase the array's theoretical advantage.

TT-Metal-style ownership

Name the controller and the working engine for every data transformation

TT-Metal is easy to reason about because its architecture names both sides of each action: a baby RISC-V dispatches work, while a NoC, unpacker, FPU/SFPU, or packer performs it. An implementable ACiM architecture needs the same precision instead of grouping everything under "the analog tile."

Controller versus working engine

Tenstorrent documents five baby RISC-V roles per Tensix: Data Movement 0, Data Movement 1, Unpack, Math, and Pack. These processors mainly dispatch and synchronize dedicated peripherals. Likewise, an ACiM tile should distinguish the firmware or state machine that issues an action from the DMA, formatter, row driver, memory array, ADC, or SIMD engine that actually transforms the data.

Equivalent execution pipelinesEach box names the controller first and the working storage or engine second.

TT-Metal

SourceDRAM / remote L1Tensor pages

ControllerDM0 baby RISC-VNoC0 reader moves pages

StorageL1 circular bufferTiled producer/consumer queue

Controller + engineUnpack RISC-V + unpackerCB tile to source registers

Controller + engineMath RISC-V + FPU/SFPUMatrix or vector arithmetic

Controller + enginePack RISC-V + packerDestination registers to output CB

ControllerDM1 baby RISC-VNoC1 writer moves result

DestinationDRAM / next TensixStored or forwarded tiles

ACiM

SourceHost / LPDDR / sensorQuantized activation block

Controller + engineTile controller + DMA/NoCMove activation to local tile

StorageLocal SRAM / input queueArray-native row and phase order

Controller + engineInput sequencer + formatter/driverBits, pulses, duration, or levels

Working engineFlash array + column networkCell multiply and column accumulate

Working engineReadout + ADCAnalog result to digital code

Controller + engineDigital scheduler + SIMD/DSPSigned, slice, partial-sum, epilogue math

DestinationOutput SRAM + DMA/NoCNext tile, LPDDR, or host

Execution stage	TT-Metal documented owner	Required ACiM owner	Data before → after	Mythic public status
1. Dispatch	Host command queue and device dispatch, followed by reader/compute/writer kernels.	Host runtime, device scheduler, and tile RISC-V or equivalent controller.	Graph invocation → validated tile commands	Partial RISC-V and dataflow scheduling are disclosed; command queues and firmware ABI are not.
2. Input transfer	DM0 baby RISC-V issues NoC0 reads into L1 circular buffers.	DMA/NoC mover controlled by a tile or global scheduler.	External activation layout → local SRAM block	Partial SRAM and router are disclosed; DMA ownership and queue protocol are not.
3. Local buffering	L1 circular buffers expose reserve, push, wait, and pop producer/consumer semantics.	Input/output queues or ping-pong SRAM banks with credits and events.	Transferred bytes → array-consumable block	Unknown SRAM exists, but public buffer topology, bank map, and synchronization primitives are absent.
4. Input formatting	Unpack baby RISC-V dispatches the unpacker to move tiles into compute source registers.	Formatter, bit-plane generator, input registers, and row driver controlled by an input sequencer.	Integer activation block → physical row-drive phases	Partial Historical digital input approximation is disclosed; exact owner, format, and timing are not.
5. Bulk compute	Math baby RISC-V dispatches matrix FPU or vector SFPU operations.	ACE-local sequencer fires the programmed conductance array and column network.	Row signals + resident weights → analog column results	Documented primitive ACE stores weights and performs matrix multiplication; the internal sequencer is not disclosed.
6. Conversion	Digital destination registers remain inside the compute path before packing.	Sample/integrate circuit, ADC or comparator, and output-code registers.	Analog column state → bounded digital codes	Partial ADC readout is disclosed historically; lane sharing, range modes, and register interface are not.
7. Reconstruction	Math and Pack paths produce the final tile format; SFPU handles supported vector work.	SIMD, DSP, fixed logic, or controller-assisted code for signed subtraction, shift/add, K reduction, scale, bias, and activation.	ADC codes → framework-equivalent output values	Unknown allocation SIMD is disclosed, but exact reconstruction ownership and accumulator contract are not.
8. Output transfer	Pack writes an output circular buffer; DM1 issues NoC1 writes to DRAM or another core.	Output SRAM/queue, egress DMA/NoC mover, completion barrier, and consumer event.	Local output block → next tile or host tensor	Partial SRAM and router are disclosed; output queue, mover, ordering, and event semantics are not.

KnownWhere bulk math happensThe ACE flash array and analog circuits store weights and perform matrix multiplication. The RISC-V and SIMD are separate digital blocks.

Reasonable architectureHow it should be controlledA tile controller issues coarse descriptors; dedicated sequencers and movers own repetitive timing and transfers; SIMD/DSP owns explicit digital reconstruction.

Still requiredWhich exact block owns each boundaryThe hardware team must publish registers, queues, formats, events, SRAM maps, converter resources, timing hazards, and telemetry.

Minimum executable hardware contract

Information needed to turn the owner map into compiler, firmware, and runtime code

TileResourceDescriptorEnumerate working enginesArray regions, SRAM banks, DMA channels, NoC ports, input formatters, row drivers, ADC groups, SIMD/DSP units, controllers, and reset domains.

MvmCommandDefine one launch descriptorWeight handle, input/output addresses, K/N ranges, input encoding, sign and slice mode, ADC range, phase count, accumulator target, dependency, and completion event.

BufferLayoutSpecify every data formHost tensor, transfer block, SRAM layout, row-drive order, bit planes, ADC-code packing, accumulator width, final tensor layout, alignment, and padding.

EngineScheduleState legal overlap and hazardsWhich DMA, array, ADC, SIMD, and NoC operations can overlap; which share banks, converters, power rails, command FIFOs, or calibration state.

SyncProtocolName producer and consumer rulesQueue depth, reserve/publish/wait/release operations, memory barriers, events, timeouts, cancellation, reset, and behavior after partial completion.

PerformanceCountersMake ownership debuggableController busy, input-starved, SRAM conflict, row-drive, array-active, ADC-busy, saturation, retry, SIMD-busy, NoC-stall, output-blocked, power, and temperature counters.

Why the unknown labels matter: a software stack cannot safely decide tiling, double buffering, prefetch, queue depth, or overlap until these ownership and resource contracts are measured or specified. A simulator may begin with explicit assumptions, but the production compiler must target the real data path. TT-Metalium architecture guide | TT-Metalium MatMul example | Mythic M1076 product brief

Mapping a real layer

Array dimensions determine which results concatenate and which must be added

The compiler must distinguish four independent decompositions. Confusing an N shard with a K shard produces the wrong graph even when every local MVM is correct.

Split N: output columnsConcatenateEach array stores a different group of output columns and receives the same activation slice. Outputs represent distinct channels and are joined side by side.

Split K: reduction rowsAdd partial vectorsEach array stores a different K range for the same output channels. Its result is incomplete until a digital accumulator adds every K contribution.

Split B: batch or tokensRepeat or replicateReuse one resident weight mapping over time, or duplicate weights onto additional arrays to process independent vectors concurrently.

Split precisionShift, scale, and addSpatial weight slices or temporal input phases produce weighted fragments. Digital reconstruction aligns each fragment before summation.

Example: A[2,3072] x W[3072,4096]Hypothetical logical array capacity: 1024 rows by 1024 columns

W blocks

N0

N1

N2

N3

K0

W00

W01

W02

W03

K1

W10

W11

W12

W13

K2

W20

W21

W22

W23

1Tile the weight matrixceil(3072/1024) x ceil(4096/1024) = 3 x 4 = 12 logical weight blocks, before sign and bit-slice expansion.

2Slice and broadcast one input rowSplit A[b,:] into K0, K1, and K2. Broadcast each slice to the four arrays in its K row.

3Run twelve local MVMsWith enough independent hardware they can run in parallel; otherwise schedule waves under ADC, NoC, SRAM, power, and thermal constraints.

4Reduce along KFor each N group, add P0n + P1n + P2n into one 1024-element output block.

5Concatenate along NJoin the four reduced blocks to form one 4096-element row of C.

6Handle B=2Repeat for the second row or use a replicated weight mapping. Then stack both result rows into C[2,4096].

Input slicesx[K0], x[K1], x[K2]Per-inference data

12 resident blocksW[k,n]Array-local MVMs

K reductionsy[n] = Σ_kP[k,n]Four digital partial-sum accumulators

N concatenatey = [y0 | y1 | y2 | y3]One 4096-element output vector

Convolution

Filters become matrix columns

Flatten each receptive-field patch across kernel height, kernel width, and input channels into a K-vector. Map output-channel filters to N columns. Stream patches as repeated MVM inputs, then reshape output vectors back to spatial feature maps.

Transformer

Linear projections dominate the analog-friendly part

Q, K, V, output, and MLP projections are dense MatMuls and can use the same decomposition. Attention score MatMul, softmax, normalization, dynamic KV-cache access, and control generally require the digital companion or another engine.

Mythic's mapping patent describes partitioning coefficients across multiple arrays, applying inputs, combining outputs, positive/negative paths, multi-row inputs, and serial multi-step input handling. NeuRRAM independently demonstrates the same system need: layers larger than an array are segmented across cores, with intermediate buffers and partial-sum accumulation outside the array in the reported prototype. Mythic mapping patent | NeuRRAM measured-silicon paper

Communication limits and asynchronous execution

More array tiles can reduce performance after the NoC saturates

Resident weights remove repeated weight fetches, but activations, ADC codes, partial sums, outputs, commands, and synchronization still move. The compiler must therefore treat NoC links, router ports, SRAM banks, and consumers as bounded resources rather than assuming that every mapped array can fire simultaneously.

NoC: packet fabric connecting on-chip blocks DMA: transfer engine that moves blocks without CPU copies VC: logical queue sharing a physical NoC link Backpressure: a full downstream resource makes upstream senders wait Credit: permission proving that destination capacity is available Barrier / event: ordering or completion condition between asynchronous operations

Short answer: async hides latency; it does not create bandwidth

Let R_offered be activation fan-out, partial-sum, output, command, and event traffic injected per second. When it approaches the effective rate of the busiest link, router output, SRAM port, or consumer, queues grow. Once buffers fill, backpressure stalls DMA and tile controllers. Double buffering can absorb a temporary mismatch, but a sustained R_offered ≥ R_service remains a bandwidth problem.

Split M: independent rows or tokens Usually the least cross-core communication Each shard computes different output rows. This is attractive when batch or token parallelism exists, but autoregressive LLM decode often has only one current token per sequence.

Split N: output columns Activation fan-out Every N shard needs the same K activation slice. Multicast reduces repeated source injection, although replicated traffic still consumes branch links and receiver bandwidth.

Split K: reduction rows Partial-sum traffic Every K shard emits an incomplete result for the same output channels. Those vectors must meet at local accumulators, a reduction tree, or a shared digital engine.

Split precision More phases and fragments Input bits, signed paths, or weight slices can generate several ADC result fragments. Reconstruct them near the array or pay extra NoC traffic and synchronization.

Traffic created by a P_K x P_N weight mapping N partitioning fans one activation slice outward; K partitioning brings partial results back together.

Source SRAMx[K0], x[K1], x[K2]One input vector

→Multicast each K slice across N

Arrays

N0

N1

N2

N3

K0

W00

W01

W02

W03

K1

W10

W11

W12

W13

K2

W20

W21

W22

W23

→Reduce partials along K

Digital reductiony[n] = P0n + P1n + P2nFour final N blocks

A useful first-order model is traffic = activation fan-out + K-partial reductions + final outputs + protocol overhead. Small tiles increase headers, descriptors, events, and barriers per useful byte; poor placement adds long shared routes and hotspots.

How congestion becomes an array stall A correct bounded design normally slows producers instead of dropping tensor data.

1Many producers issue trafficDMA reads, multicast, partial sums, outputs, commands

2A shared resource saturatesNoC link, router output, destination SRAM port, ADC or reducer

3Queues and circular buffers fillOutstanding requests can no longer retire at the issue rate

4Backpressure moves upstreamWriters lose credits; DMA and dispatch wait

5The compute pipeline bubblesArray is input-starved or output-blocked; latency and energy rise

Safe overlap

Bound every asynchronous pipeline with ownership, completion, and credits

Desired steady-state overlapDifferent tiles occupy independent engines at the same time.

Enginet0t1t2t3

Input DMATile 0Tile 1Tile 2Tile 3

MVM + ADCTile 0Tile 1Tile 2

SIMD / reduceTile 0Tile 1

Output DMATile 0

T_tile ≥ max(T_input, T_MVM+ADC, T_digital, T_output) only when those stages use sufficiently independent resources. Shared NoC links couple input and output time.

One bounded producer-consumer transactionPublish validity only after payload completion.

1Reserve destination slotConsumer credit proves SRAM capacity exists.

2Issue async DMA / NoC transferKeep the source and destination buffers alive.

3Wait or record completionA transfer barrier orders the payload before its ready event.

4Publish tile-readyThe array sequencer may now consume the slot.

5Complete MVM, ADC, and digital workRecord consumer-done after the last read or write.

6Release and reuseReturn the credit; only now overwrite the ping-pong slot.

Problem	What goes wrong	Observable symptom	Implementation control
Activation fan-out	Repeated unicast injects the same K slice once per N shard.	Source link or SRAM-read port saturates while receivers remain unevenly utilized.	Multicast once, place receivers along short routes, and reserve every receiver before transmission.
K-partial convergence	Many arrays send vectors to one reducer or output SRAM bank.	Reducer busy, destination-bank conflicts, output-blocked array cycles.	Reduce locally, use a tree, distribute accumulators, and fuse scale or epilogue before egress.
Too many small tiles	Headers, descriptors, events, and barriers dominate useful payload.	High command rate and low payload bandwidth despite busy routers.	Coalesce transfers, enlarge useful work per launch, cache command templates, and avoid unnecessary precision fragments.
Burst synchronization	All cores inject at the same phase and contend for the same links.	Periodic queue-depth spikes and long tail latency.	Schedule waves, stagger launches, cap in-flight work, or map traffic across independent routes.
Early consumption	The controller starts MVM before an asynchronous transfer completes.	Nondeterministic wrong outputs or stale activation data.	Wait on a completion event; order payload writes before publishing tile-ready.
Premature reuse	A producer overwrites a ping-pong slot still owned by DMA or compute.	Intermittent corruption that changes with timing or profiling.	Reserve/publish/wait/release semantics, bounded credits, and explicit buffer lifetimes.
Cross-path reordering	Data and notification use NoCs or virtual channels without a common ordering guarantee.	Ready flag observed before payload arrival.	Use documented same-path ordering where valid; otherwise add explicit NoC barriers and device events.
Cyclic wait	Producers hold one resource while waiting for credits owned by one another.	No forward progress, timeout, or watchdog reset.	Use a global acquisition order, separate traffic classes, bounded queues, timeout diagnostics, and reset recovery.
Excess synchronization	A barrier is placed after every operation, serializing independent engines.	Correct results but little DMA/MVM/output overlap.	Synchronize at ownership boundaries and true hazards, then verify overlap with timestamped counters.

CompilerModel communication, not just MAC countEstimate bytes and routes for N fan-out, K reductions, precision fragments, outputs, and protocol overhead. Reject mappings whose busiest link or destination exceeds a measured utilization budget.

Runtime and firmwareKeep async work boundedUse command-queue limits, credits, dependency events, transfer barriers, cancellation, timeouts, and deterministic recovery instead of allowing unlimited outstanding descriptors.

HardwareExpose traffic classes and telemetryProvide multicast, adequate virtual channels, distributed reducers, bank-aware SRAM access, queue-depth and stall counters, and independent paths where overlap is expected.

ProfilerIdentify the resource that stopped progressCorrelate NoC bytes, link utilization, queue high-water marks, DMA busy, input-starved, output-blocked, reducer busy, and array-active cycles under one execution ID.

Evidence boundary: Tenstorrent publicly documents asynchronous NoC operations, program order for requests on the same NoC and the same virtual channel, no ordering guarantee across different NoCs or virtual channels, and a semaphore-based multicast MatMul pattern in which receivers reserve space before the sender transmits. Applying those mechanisms to ACiM is a design inference: the exact Mythic or iHW queue, route, barrier, and virtual-channel implementation is not public. TT-Metal NoC ordering | TT-Metal multicast MatMul lab | TT-Metal asynchronous queues and events

Interactive architecture map

Trace the complete signal path

Select a layer to see its responsibility, dominant failure mode, mitigation pattern, evidence, and interview prompt.

Mythic case study

The disclosed M1076 tile separates bulk analog math from digital orchestration

The product brief says every tile is driven by a Mythic ACE containing flash weight storage and analog matrix-multiplication circuits, beside a RISC-V nano-processor, SIMD processor, SRAM, and NoC router. The exact internal command and reconstruction boundary is not public, so the responsibilities below distinguish documented blocks from the architectural role they are best suited to perform.

Mythic ACE Embedded flash stores resident weights Cells and columns perform bulk MVM Input drive, sensing, and ADC form the mixed-signal boundary

Local SRAMPer-inference activations, outputs, descriptors, and temporary state

16-bit SIMDDigital vector and post-processing work; exact operator allocation is not public

32-bit RISC-VTile sequencing and control, not the bulk array MACs

NoC routerMoves activations, results, commands, and events between tiles

Known versus current roadmap

The M1076 block structure and first-generation product figures are publicly documented. Mythic's 2025-2026 claims for 120 TOPS/W, LLM scale, and roughly 100x system advantages are company roadmap and internal benchmark statements. They should not be presented as independently reproduced measurements.

Mythic's May 2026 Videantis acquisition also makes the hybrid boundary explicit: analog for dense AI matrix operations, unified digital compute for attention, signal processing, codecs, SLAM, control, and programmability.

Follow the controller-to-array execution sequence

Hardware-software co-design

The model reaches the array through a compiler pipeline

1TrainPyTorch or another standard framework

2QuantizeFP32 to ANA8; choose scales and ranges

3HardenQAT or analog-aware retraining where needed

4PartitionMap matrices and digital operators to tiles

5ScheduleAllocate buffers, routes, and dataflow tasks

6ValidateMeasure accuracy, latency, power, and corners

The correct mental model is an analog MVM accelerator inside a digital system. The compiler and calibration stack determine tensor ranges and placement; the analog array supplies dense parallel arithmetic; digital units preserve generality and precision where the array is a poor fit.

Technology comparison

Flash is one member of a broader CIM design space

Similar matrix equations hide different density, write, drift, endurance, integration, and readout tradeoffs.

System	Memory	Weight representation	Input / output path	Best fit	Main caveat

Reading order

Four documents that reveal different layers

Product

M1076 product brief

Use it for the tile blocks, capacity, interfaces, peak compute, and product positioning. Treat performance comparisons as vendor claims.

Open product brief

Primitive

Hot Chips 2018

Use it for the flash-resistor mental model, ADC boundary, digital input approximation, and weight-memory argument.

Open presentation

Mapping

Matrix mapping patent

Use it to study positive and negative lines, oversized inputs, serial steps, array regions, and output aggregation.

Open patent

Independent comparison

NeuRRAM and IBM chips

Use measured RRAM and PCM systems to understand calibration, converters, hardware-aware training, and complete-system boundaries.

Open evidence ledger

Primary sources

Architecture source ledger

Company material establishes what Mythic discloses; peer-reviewed measured-silicon work supports cross-company technical comparison.

Mythic and Analog Compute-in-Memory Architecture

AiCM, AIMC, AiMC, and analog CIM

One matrix-vector multiply in five steps

Cells are linear and independent

Weights stay where programmed

Readout preserves information

A framework MatMul becomes repeated analog matrix-vector operations

Short answer: where does the MatMul happen?

Three control timescales turn one graph operation into array pulses

Name the controller and the working engine for every data transformation

Controller versus working engine

Information needed to turn the owner map into compiler, firmware, and runtime code

Array dimensions determine which results concatenate and which must be added

Filters become matrix columns

Linear projections dominate the analog-friendly part

More array tiles can reduce performance after the NoC saturates

Short answer: async hides latency; it does not create bandwidth

Bound every asynchronous pipeline with ownership, completion, and credits

Trace the complete signal path

The disclosed M1076 tile separates bulk analog math from digital orchestration

Known versus current roadmap

The model reaches the array through a compiler pipeline

Flash is one member of a broader CIM design space

Four documents that reveal different layers

M1076 product brief

Hot Chips 2018

Matrix mapping patent

NeuRRAM and IBM chips

Architecture source ledger