Interview Study for Mythic and Analog CIM Teams

Signal integrity becomes numerical accuracy

Prepare: MOS operation, noise, mismatch, PVT, current mirrors, integrators, comparators, ADC/DAC architectures, references, calibration, layout effects, Monte Carlo, and Verilog real-number models.

Be ready to design: a column readout with a stated range, ENOB, settling time, power budget, calibration path, and corner plan.

Make a probabilistic primitive behave like a system block

Prepare: pipelines, SRAM, NoCs, dataflow, fixed-point arithmetic, power and clock domains, RISC-V/SIMD roles, performance modeling, SystemVerilog, UVM, RNM, assertions, and coverage.

Be ready to design: a tile scheduler and verification plan that covers analog latency, backpressure, saturation, faults, reset, and power transitions.

Turn graph semantics into fixed physical resources

Prepare: modern C++ and Python, SSA/graph IR, ONNX, MLIR/LLVM, TVM/XLA/IREE concepts, lowering, fusion, tiling, scheduling, memory allocation, quantization, error injection, and heterogeneous partitioning.

Be ready to design: an IR and cost model for array shapes, ADC phases, partial sums, local SRAM, digital fallback, and route pressure.

Prove the chip across units, corners, and time

Prepare: bring-up, characterization, ATE, wafer sort, yield analysis, correlation, guardbands, binning, screening, DFT/MBIST, failure analysis, reliability, automation, and statistical data analysis.

Be ready to design: a test flow that separates device defects, analog variation, digital logic faults, package effects, and model-level escapes.

Model the signal chain

1. Start with an FP32 matrix-vector reference.
2. Quantize weights and activations with explicit scales.
3. Map signed weights to differential conductances.
4. Add programming error, drift, read noise, IR drop, clipping, and ADC quantization one at a time.
5. Measure MVM error and model accuracy across random seeds and time.

Pay for every recovery

1. Compare per-tensor and per-channel scaling.
2. Add write-verify or measured-error calibration.
3. Try noise-aware fine-tuning.
4. Route one sensitive layer to a precise digital path.
5. Report extra cells, cycles, conversions, digital operations, and calibration frequency.

Derive analog MVM from first principles.

State V-to-input and G-to-weight mappings, derive cell current and column sum, then list the linearity, independence, range, and readout assumptions.

Why is ANA8 not simply ordinary INT8?

Separate quantization error from analog programming/read error, explain calibration and analog-aware retraining, and define the digital reference.

Map a 4096 by 4096 projection onto 1024 by 1024 arrays.

Find the 4 by 4 partition, explain broadcast and partial-sum reduction, account for signed and bit-sliced representation, then identify bottlenecks.

Choose ADC precision for a layer.

Use output distribution, signal range, noise floor, clipping budget, ENOB, area/energy, conversion phases, and model sensitivity rather than naming a bit count.

Accuracy drops after one week in the field.

Reproduce by chip and temperature, compare reference paths, separate common gain drift from per-cell drift, test recalibration, and check whether model margins changed.

Verify a digital controller around an analog array.

Define a real-number model, bounded error contract, saturation and latency behavior, randomized PVT/error distributions, assertions, coverage, and transistor-level correlation.

Partition a transformer between analog and digital compute.

Favor dense projections for analog; evaluate outlier-sensitive early/output layers; leave softmax, normalization, dynamic indexing, and control on flexible digital units.

Did Nature prove accuracy is solved?

Say no as a universal claim, then cite one measured success, its baseline and mitigation, one open issue, and the end-to-end experiment needed to generalize it.