Mythic says analog will execute efficient matrix operations while Videantis digital cores handle control, attention, non-max suppression, codecs, SLAM, and other high-performance work.
Company case study | research snapshot 2026-07-11
Mythic and Videantis: What the Acquisition Solves
Mythic acquired Videantis GmbH on May 19, 2026. The deal adds a production-proven digital processor architecture and software stack to Mythic's analog compute-in-memory platform. That can make the system complete and create a digital path for sensitive operations, but it is not evidence that flash-cell error, converter error, drift, aging, or analog effective precision has been eliminated.
MythicAnalog flash for dense matrix operations
VideantisProgrammable digital processing and mature tools
Strategic valueComplete hybrid execution and faster productization
Evidence gapNo public post-deal silicon accuracy benchmark yet
Research verdict
A strong system acquisition, not a demonstrated cure for analog error
The best-supported interpretation is build-versus-buy for the digital half of a hybrid computer. Mythic already used digital SRAM, SIMD, RISC-V control, routing, conversion, calibration, and compilation around analog matrix engines. Videantis adds a much broader VLIW/SIMD processor, explicit memory control, complete-network execution, a compiler/SDK, simulation and debug tools, and automotive production experience. This can contain accuracy-sensitive work in digital execution, but the companies have not published the partition policy, numerical contract, calibration interface, or measured post-acquisition results.
A compiler could route sensitive layers or unsupported operators to deterministic digital cores. The public announcement does not confirm that this sensitivity-based policy exists.
No public report gives same-model digital-INT8 versus hybrid accuracy across multiple chips, temperature, voltage, calibration age, device age, and analog coverage.
Company disclosure
Independent or academic source
Engineering inference
Public paper boundary
As of July 11, 2026, this review found Mythic architecture presentations, product documentation, software documentation, demonstrations, press releases, and trade reporting, but no peer-reviewed Mythic silicon paper publishing end-to-end model accuracy across chip populations, PVT corners, calibration age, and device aging. Related flash-CIM papers explain plausible techniques, but they are not proof of Mythic's proprietary design.
Mythic execution flow chart
Separate the disclosed analog-flash path from the proposed hybrid platform
Mythic has disclosed graph conversion, analog-aware optimization, flash weight programming, analog MVM, ADC readout, and digital tile support. The acquisition announcement discloses the intent to combine those engines with Videantis cores. It does not disclose the unified runtime, partition cost model, or recovery protocol drawn below.
Disclosed model and compiler path
Flash programming and calibration
Proposed hybrid inference
Required health and fallback loop
- 1Import graphFramework or ONNX model and reference accuracy
- 2Set rangesQuantization, clipping, calibration data, ANA8 target
- 3Analog-aware adaptRetraining for supported analog execution
- 4Map graphAnalog matrices, digital tile work, tensor layout
- 5Pack and generateWeight image, commands, code, deployment artifact
- 6QualifyCompare converted model with the named digital baseline
- 1Select tilesCapacity, supported matrix shapes, healthy resources
- 2Program flashMap weights into multilevel conductance targets
- 3Verify or refreshCompare physical state with stored digital truth
- 4CalibrateAnalog/digital correction, converter range, PVT state
- 5Bind artifactDevice identity, programmed image, calibration version
- 1Digital prepareVideantis control, normalization, layout, scale, routing
- 2Choose targetAnalog coverage, sensitivity, deadline, locality, health
- 3Drive inputsRange-controlled activation bits or phases enter the tile
- 4Flash MVM and ADCConductance MAC, integration, conversion, status
- 5Digital finishAccumulate, attention, nonlinear, codec, SLAM, control
- 6Apply policyAccept, repeat, recalibrate, refresh, or run digitally
Required closed loop
Converter and tile telemetry → accuracy/health policy → calibration or flash refresh → sensitivity-aware digital fallback → auditable device-state update
Evidence boundary: the individual Mythic and Videantis building blocks are disclosed, and the acquisition announcement states the hybrid intent. The sequence below is a testable engineering model for integration. Until Mythic publishes the unified compiler/runtime and measured combined silicon, it must not be cited as the behavior of a shipping product.
Proposed Mythic-Videantis sequence diagram
One request needs one owner for analog accuracy and digital fallback
The critical interface is not only a command queue. It carries numerical ranges, calibration identity, health state, placement rationale, and the cost of crossing from analog to digital execution.
ApplicationModel and request
Unified runtimeProposed owner
Videantis coresDigital execution
Mythic tileFlash MVM and ADC
Calibration controlDevice-bound state
- Load, program, and bind
- Load hybrid artifact and reference policy
- Query device, programmed state, calibration, and health
- Program/refresh flash and calibrate tile
- Return bound device state to runtime
- Request and repeated graph-region loop
- Submit input and latency/accuracy policy
- Run control, preprocessing, and partition decision
- Execute unsupported, sensitive, dynamic, and control work
- Send matrix command, activation phases, range, and calibration ID
- Input phases → flash MVM → integrate → ADC
- Return output, saturation, converter, and health status
- Rescale, accumulate, finish operator, and continue graph
- Return region result, coverage, and measured cost
- Only when health or numerical policy fails
- Request recalibration, refresh, remap, or quarantine
- Return updated state or reject analog coverage
- Rerun rejected region with deterministic digital fallback
- Return output, trace, coverage, and health status
Mythic-specific bottleneck map
Videantis can remove system gaps, but it can also expose the true analog cost
The acquisition helps most with flexible compute, scheduling, memory control, tools, and productization. Flash programming, converter quality, calibration, retention, and analog effective precision remain Mythic responsibilities. Boundary traffic and excessive fallback can erase the claimed analog advantage.
| Bottleneck | Why it matters for Mythic | What Videantis can contribute | What still must be proved |
|---|---|---|---|
| Flash programming precision | Mapping a weight to one of many conductance levels introduces programming spread and cell-dependent error before inference begins. | Nothing at the device level; digital cores can orchestrate programming, verification, remapping, and fallback. | Production distributions, write-verify policy, failed-cell handling, programming time, energy, yield, and capacity loss. |
| Retention, drift, and refresh | Stored analog state changes with time and environment, so model correctness has a calibration age and refresh history. | Health-vector execution, deterministic maintenance scheduling, telemetry, and a digital path while arrays are refreshed. | Refresh trigger, interval, accuracy recovery, downtime, endurance consumption, field policy, and lifetime corners. |
| ADC effective precision | Digitization follows every analog MVM. Offset, nonlinearity, noise, range, PVT, and saturation can set the real accuracy ceiling. | Range analysis, output correction, sensitive-region fallback, profiling, and software-visible status handling. | ENOB, INL/DNL, noise, offset, saturation rate, converter energy/area, chip variation, temperature, voltage, and aging. |
| Input-bit or phase delivery | Applying multibit activations over separate phases can serialize work and repeatedly charge array lines. | Input preparation, sparsity, scheduling, overlap, local buffering, and deterministic phase control. | Actual phase count, activation precision, DAC/input energy, overlap efficiency, utilization, and latency per mapped layer. |
| MVM dynamic range | Eight-bit weights do not imply an eight-bit dot-product result; long reductions can clip or lose small contributions. | Per-layer scaling, outlier routing, high-precision digital accumulation, extra passes, and digital execution for narrow error budgets. | Accumulator precision, output ranges, partial-sum policy, saturation statistics, model sensitivity, and correction energy. |
| Analog/digital boundary traffic | Every fallback or hybrid split may require conversion, SRAM storage, NoC transport, synchronization, and format changes. | Explicit memory management, multicore scheduling, local-data placement, fusion, and deterministic communication. | Bytes and conversions per inference, boundary latency/energy, buffer capacity, contention, and whether overlap hides the cost. |
| Digital fallback dilution | Fallback protects accuracy, but too much Videantis execution can reduce analog coverage and erase the energy advantage. | Efficient deterministic execution and a graceful path for unsupported or sensitive work. | Analog coverage by model and layer, fallback frequency, quality recovery, total energy, latency, area, and breakeven point. |
| Attention and KV state | Dynamic attention, normalization, softmax, control, and KV-cache traffic do not match static weight-stationary flash MVM cleanly. | Programmable VLIW/SIMD execution, memory control, and complete-network processing. | Memory hierarchy, KV capacity/bandwidth, long-context scaling, attention latency, and end-to-end LLM evidence. |
| Model loading and updates | Flash writes are slower and less update-friendly than ordinary SRAM or DRAM model loading. | Transactional deployment, digital adapters, staged rollout, rollback, and host/runtime control. | Cold-start time, update granularity, endurance, partial-write recovery, concurrent serving, and fleet rollout cost. |
| Unified compiler and runtime | Mythic and Videantis bring separate mapping assumptions, backends, tools, and performance models. | Videantis contributes mature analysis, code generation, simulation, profiling, debugging, and memory analysis. | One IR, numerical contract, partition objective, calibration ABI, debugger timeline, versioning, and ownership model. |
| Roadmap and evidence gap | Most detailed public Mythic architecture material describes older parts, while the company says it rebuilt architecture and software. | Production discipline and tools can improve reproducibility and qualification. | Post-acquisition silicon, same-model digital baseline, chip population, PVT/lifetime data, analog coverage, correction cost, and independent reproduction. |
Mythic critical path
First prove converter and flash accuracy across devices and time. Then prove that the unified compiler keeps sensitive work digital without excessive boundary traffic. Finally report end-to-end accuracy, latency, energy, analog coverage, calibration, refresh, and fallback together. A peak analog TOPS/W number cannot answer those questions.
System continuation: the scale-out, defect-tolerance, and LLM design specifies how tile harvesting, row/column repair patterns, logical meshes, collectives, KV memory, digital attention, and recovery fit into one compiler/runtime contract.
Public record
The architecture evolved from an analog accelerator toward a hybrid platform
Mythic presented embedded-flash matrix memory, 8-bit weight levels, ADC output, digital input approximation, SRAM, SIMD, RISC-V, and a tile network.
Mythic described more than 27,000 converters, 8-bit conversion targets, internal variation handling, and ResNet-50 operation near a digital INT8 baseline.
The 76-tile device advertised 25 TOPS, 80 million weights, 3-4 W typical model power, pre-qualified networks, and no external DRAM for model weights.
Mythic raised $125 million and stated that it had rebuilt its architecture, roadmap, software, and strategy. New performance figures were identified as internal benchmarks.
Honda announced investment and joint automotive-SoC development, combining Honda models and ECU expertise with Mythic's analog CIM and SDK work.
Mythic bought the German processor-IP company and retained all five founders. Financial terms were not disclosed in the public announcement.
Mythic accuracy stack
Public disclosures show several correction layers, but not a complete proof
Mythic has not publicly disclosed every circuit or calibration algorithm. The flow below separates stated mechanisms from the measurements that would still be required for an engineering sign-off.
| Disclosed mechanism | Problem it addresses | What is publicly supported | Remaining evidence gap |
|---|---|---|---|
| 8-bit flash weight representation | Maps a digital model into dense nonvolatile analog storage. | Hot Chips material describes 256 levels per weight and conductance-based multiplication. | No public distribution of programmed error, retention, endurance, or effective bits across production chips. |
| Refresh from off-chip true values | Can restore weights after drift or retention loss. | Mythic's 2018 explanation explicitly says flash resistance can be refreshed from stored truth. | Refresh interval, detection policy, write cost, downtime, endurance, and field telemetry are not disclosed. |
| Compact high-speed 8-bit conversion | Limits quantization error at the analog/digital boundary. | Mythic reported designing and production-testing tens of thousands of on-chip ADC/DAC elements. | No public INL, DNL, ENOB, offset, noise, temperature, voltage, yield, or aging tables. |
| Internal analog and digital calibration | Compensates mismatch, manufacturing variation, and environmental change. | Company statements and independent trade reporting describe calibration as central to reaching the 8-bit target. | The calibration equations, per-chip state, runtime triggers, cost, and failure policy remain proprietary. |
| Range setting, quantization, and retraining | Avoids clipping and makes the model robust to low-precision execution. | Public descriptions show an offline graph-to-analog-INT8 compilation path and pre-qualified models. | No complete public model table reports baseline, converted accuracy, analog accuracy, and calibration conditions. |
| Digital support inside each tile | Executes control and operations for which analog MVM is unsuitable. | M1076 documentation lists RISC-V, SIMD, SRAM, and NoC resources beside every analog engine. | The supported-operator list, fallback precision, conversion traffic, and accuracy impact are not public. |
"INT8 accuracy" is not "perfect 8-bit analog arithmetic"
A model can finish close to a digital INT8 baseline even when individual analog operations have fewer effective bits, because quantization, calibration, retraining, error averaging, and digital execution can absorb some error. A valid proof must report task accuracy against the same digital baseline and also expose effective precision, saturation, chip variation, PVT, retention time, calibration age, and correction cost.
What Mythic bought
Videantis contributes the programmable digital system around the analog engine
VLIW plus SIMD unified cores
Scalable identical cores execute deep learning, classical vision, signal processing, imaging, video, attention, non-max suppression, and SLAM.
Accuracy relevance: deterministic digital execution is a natural home for sensitive, nonlinear, control-heavy, and unsupported graph regions.
Compiler, SDK, simulator, and debug
The v-NN SDK performs data-type analysis, dataflow analysis, graph partitioning, multicore mapping, and optimization. The tool suite includes a C compiler, code generation, simulation, profiling, debugging, coverage, and runtime memory analysis.
Accuracy relevance: the tools can host a future sensitivity-aware hybrid partitioner, but the Mythic integration has not been published.
Explicit memory and deterministic deployment
Videantis emphasizes local data, explicit memory management, predictable execution, automotive sign-off tooling, ASPICE history, and deployed processor IP.
Accuracy relevance: repeatable scheduling and observability improve validation, but field reliability of prior digital IP does not prove the new analog subsystem's numerical accuracy.
Important boundary: Videantis does not publicly claim a flash-programming, ADC-calibration, analog-noise, or drift-remediation technology. It solves digital completeness, programmability, data movement, tooling, and productization. Any direct benefit to analog model accuracy comes through partitioning, fallback, orchestration, and validation, unless Mythic later discloses a deeper integration.
Build-versus-buy analysis
The acquisition is strategically coherent because it buys time, software, and production discipline
Analog MVM and programmable digital execution solve different workload regions and share a data-locality philosophy.
Mythic obtains roughly two decades of processor-IP work, a mature toolchain, founders, and deployed automotive experience instead of rebuilding all of it.
Digital fallback and partitioning can reduce exposure to analog error, but no public combined benchmark proves the gain.
Videantis does not directly remove flash drift, programming spread, ADC/DAC nonlinearity, PVT sensitivity, noise, or aging.
Tooling, deterministic execution, existing production programs, and safety-process experience align with the Honda SoC schedule.
The public announcement does not disclose purchase price, consideration, revenue, integration cost, or financial targets.
| System problem | Mythic before the deal | Videantis contribution | Assessment |
|---|---|---|---|
| Dense matrix energy | Embedded-flash analog MVM. | Orchestration and surrounding digital work. | Mythic remains the primary solution. |
| Attention, NMS, SLAM, codecs, control | Small SIMD/RISC-V resources and host execution. | Scalable VLIW/SIMD cores and software libraries. | Direct and explicitly stated acquisition benefit. |
| Accuracy-sensitive graph regions | Calibration, conversion, digital support, and model qualification. | Potential deterministic fallback target. | Strong engineering inference; public policy and results are missing. |
| Graph partitioning and scheduling | Proprietary Mythic compiler flow. | v-NN data-type/dataflow analysis and multicore mapping. | Promising, but the unified IR and cost model are undisclosed. |
| On-chip data movement | Tile SRAM and NoC. | Explicit memory management, hierarchical storage, and intelligent scheduling. | Can reduce boundary traffic if the analog/digital interface is co-designed. |
| Flash, ADC, PVT, drift, aging | Mythic analog design, calibration, refresh, and software compensation. | No disclosed device-level solution. | Not solved by the acquisition itself. |
| Automotive deployment | Honda co-development and Mythic SDK experience. | Long production history, sign-off tools, ASPICE experience, and automotive customers. | Major schedule and execution-risk reduction, but the new hybrid SoC needs its own qualification. |
Why acquire instead of license?
The transaction retains all five Videantis founders and keeps Videantis as a wholly owned subsidiary. That gives Mythic control of the architecture roadmap, compiler/runtime integration, safety process, customer support, and scarce engineering knowledge. A normal IP license would provide cores and tools, but less control over the cross-layer numerical contract that a new analog-digital machine requires. This is an inference from the disclosed structure of the deal; Mythic did not publish its internal build-versus-buy analysis.
Required combined architecture
A hybrid chip needs one compiler contract, not two accelerators connected after the fact
AnalogTargetProfileMeasured capabilityPer-chip array, converter, noise, fault, PVT, energy, latency, drift, and calibration data.
NumericalContractOperator toleranceAccepted input/output range, error distribution, saturation, precision, accumulation, and fallback rule.
PartitionDecisionAuditable placementWhy each graph region runs on analog, Videantis digital, host CPU, or a rejected path.
CalibrationArtifactDeployment stateProgramming targets, scales, offsets, chip identity, temperature assumptions, age, and refresh policy.
RuntimeHealthField maintenanceSentinel results, drift score, converter health, refresh count, fallback events, and rollback status.
EvidenceReportClaim boundaryBaseline, datasets, analog coverage, chip count, conditions, accuracy delta, correction cost, and exclusions.
Source-labeled claim ledger
Separate disclosed facts, independent concerns, and reasonable inference
Flash levels and refresh
Mythic described 8-bit weights as 256 programmed flash conductance levels and stated that resistance values could be refreshed from an off-chip true copy.
Boundary: architecture disclosure, not a population/lifetime measurement.
Converters, calibration, and INT8 target
Mythic reported compact high-speed 8-bit converters, manufacturing test, variation handling, model quantization, and production intent near a digital INT8 baseline.
Boundary: no complete public benchmark table or converter characterization.
Internal calibration is essential
Independent coverage describes analog and digital calibration inside M1076 and reports Mythic's close-to-INT8 accuracy claims.
Boundary: reporting based substantially on vendor briefings, not an independent silicon reproduction.
Effective precision and aging remain disputed
Semiconductor Engineering highlights concerns around multi-level flash precision, aging, manufacturing spread, analog noise, and ADC/DAC energy.
Boundary: the article does not identify the cause of Mythic's earlier commercial setback and should not be treated as a Mythic failure analysis.
Videantis is the digital half
Mythic explicitly assigns dense matrix work to analog and flexible control, attention, NMS, codecs, SLAM, and other high-performance work to Videantis digital execution.
Boundary: combined silicon, scheduling, accuracy, and energy results were not published.
Mature mapping and validation tools
The v-NN SDK performs data-type and dataflow analysis, partitioning, and mapping. The tool suite includes simulation, profiling, debugging, coverage, memory analysis, and automotive sign-off support.
Boundary: these are digital-platform capabilities; their integration with Mythic calibration is not public.
Sensitivity-aware digital fallback is plausible
A unified compiler could route layers with narrow error budgets, converter saturation, unsupported math, or safety constraints to Videantis cores.
Boundary: plausible architecture, not a disclosed feature or measured result.
100x energy efficiency remains a claim
Mythic's 2025-2026 releases cite internal benchmarks and a 100x advantage over GPU systems; Honda independently confirms co-development and investment.
Boundary: partnership validates interest and diligence, not the advertised benchmark without public methodology and results.
What would prove the strategy
Require an ablation that measures both accuracy recovery and its digital cost
Report FP32 and production digital INT8 before any analog conversion.
Measure Mythic mapping with calibration but without Videantis fallback.
Add sensitivity-based digital placement and publish the exact analog coverage.
Disable calibration, retraining, refresh, and fallback one at a time.
Publish mean, tails, weak arrays, yield, remapping, and rejected devices.
Sweep the operating envelope and repeat before and after recalibration.
Measure drift, read disturb, refresh frequency, endurance, and field policy.
Include converters, digital cores, NoC, buffers, host traffic, and idle power.
Study and interview labs
Turn the acquisition into testable engineering work
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Sources and evidence boundaries